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module rxuart(i_clk, i_reset, i_setup, i_uart_rx, o_wr, o_data, o_break,

module rxuart(i_clk, i_reset, i_setup, i_uart_rx, o_wr, o_data, o_break,

                        o_parity_err, o_frame_err, o_ck_uart);

                        o_parity_err, o_frame_err, o_ck_uart);

        parameter [30:0] INITIAL_SETUP = 31'd868;

        parameter [30:0] INITIAL_SETUP = 31'd868;

        // 8 data bits, no parity, (at least 1) stop bit

        // 8 data bits, no parity, (at least 1) stop bit

        input   wire            i_clk, i_reset;

        input   wire            i_clk, i_reset;

        input   wire    [30:0]   i_setup;

        input   wire    [30:0]   i_setup;

        input   wire            i_uart_rx;

        input   wire            i_uart_rx;

        output  reg             o_wr;

        output  reg             o_wr;

        output  reg     [7:0]    o_data;

        output  reg     [7:0]    o_data;

        output  reg             o_break;

        output  reg             o_break;

        output  reg             o_parity_err, o_frame_err;

        output  reg             o_parity_err, o_frame_err;