Subversion Repositories wbuart32

        input   wire            i_uart_rx;

        input   wire            i_uart_rx;

        output  reg             o_wr;

        output  reg             o_wr;

        output  reg     [7:0]    o_data;

        output  reg     [7:0]    o_data;

        reg     [3:0]    state;

        reg     [3:0]    state;

        assign  half_baud = { 1'b0, CLOCKS_PER_BAUD[23:1] } - 24'h1;

        assign  half_baud = { 1'b0, CLOCKS_PER_BAUD[23:1] } - 24'h1;

        reg     [23:0]   baud_counter;

        reg     [23:0]   baud_counter;

        reg             zero_baud_counter;

        reg             zero_baud_counter;

        // a stop bit, in which case we copy the data_reg into our output

        // a stop bit, in which case we copy the data_reg into our output

        // data register, o_data, and tell others (for one clock) that data is

        // data register, o_data, and tell others (for one clock) that data is

        // available.

        // available.

        //

        //

        initial o_data = 8'h00;

        initial o_data = 8'h00;

        always @(posedge i_clk)

        always @(posedge i_clk)

                if ((zero_baud_counter)&&(state == `RXUL_STOP))

                if ((zero_baud_counter)&&(state == `RXUL_STOP))

                begin

                begin

                        o_wr   <= 1'b1;

                        o_wr   <= 1'b1;

                        o_data <= data_reg;

                        o_data <= data_reg;

        // The baud counter

        // The baud counter

        //

        //

        // This is used as a "clock divider" if you will, but the clock needs

        // This is used as a "clock divider" if you will, but the clock needs

        // to be reset before any byte can be decoded.  In all other respects,

        // to be reset before any byte can be decoded.  In all other respects,

        // intervals.

        // intervals.

        always @(posedge i_clk)

        always @(posedge i_clk)

                if ((zero_baud_counter)|||(state == `RXUL_IDLE))

                if ((zero_baud_counter)|||(state == `RXUL_IDLE))

                        baud_counter <= CLOCKS_PER_BAUD-1'b1;

                        baud_counter <= CLOCKS_PER_BAUD-1'b1;

                else

                else