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https://opencores.org/ocsvn/wbuart32/wbuart32/trunk
[/] [wbuart32/] [trunk/] [rtl/] [txuart.v] - Diff between revs 9 and 14
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Rev 9 |
Rev 14 |
Line 169... |
Line 169... |
always @(posedge i_clk)
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always @(posedge i_clk)
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q_rts <= i_rts;
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q_rts <= i_rts;
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always @(posedge i_clk)
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always @(posedge i_clk)
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qq_rts <= q_rts;
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qq_rts <= q_rts;
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always @(posedge i_clk)
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always @(posedge i_clk)
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ck_rts <= (qq_rts)&&(hw_flow_control);
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ck_rts <= (qq_rts)||(!hw_flow_control);
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initial o_uart_tx = 1'b1;
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initial o_uart_tx = 1'b1;
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initial r_busy = 1'b1;
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initial r_busy = 1'b1;
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initial state = `TXU_IDLE;
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initial state = `TXU_IDLE;
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initial lcl_data= 8'h0;
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initial lcl_data= 8'h0;
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Line 253... |
Line 253... |
// Our setup register. Accept changes between any pair of transmitted
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// Our setup register. Accept changes between any pair of transmitted
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// words. The register itself has many fields to it. These are
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// words. The register itself has many fields to it. These are
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// broken out up top, and indicate what 1) our baud rate is, 2) our
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// broken out up top, and indicate what 1) our baud rate is, 2) our
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// number of stop bits, 3) what type of parity we are using, and 4)
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// number of stop bits, 3) what type of parity we are using, and 4)
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// the size of our data word.
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// the size of our data word.
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initial r_setup = INITIAL_SETUP[30:0];
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initial r_setup = INITIAL_SETUP;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (state == `TXU_IDLE)
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if (state == `TXU_IDLE)
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r_setup <= i_setup;
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r_setup <= i_setup;
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// lcl_data
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// lcl_data
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