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[/] [wbuart32/] [trunk/] [rtl/] [txuart.v] - Diff between revs 14 and 15

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Rev 14 Rev 15
Line 110... Line 110...
`define TXU_BREAK       4'he
`define TXU_BREAK       4'he
`define TXU_IDLE        4'hf
`define TXU_IDLE        4'hf
//
//
//
//
module txuart(i_clk, i_reset, i_setup, i_break, i_wr, i_data,
module txuart(i_clk, i_reset, i_setup, i_break, i_wr, i_data,
                i_rts, o_uart_tx, o_busy);
                i_cts_n, o_uart_tx, o_busy);
        parameter       [30:0]   INITIAL_SETUP = 31'd868;
        parameter       [30:0]   INITIAL_SETUP = 31'd868;
        input                   i_clk, i_reset;
        input                   i_clk, i_reset;
        input           [30:0]   i_setup;
        input           [30:0]   i_setup;
        input                   i_break;
        input                   i_break;
        input                   i_wr;
        input                   i_wr;
        input           [7:0]    i_data;
        input           [7:0]    i_data;
        // Hardware flow control Ready-To-Send bit.  Set this to one to use
        // Hardware flow control Ready-To-Send bit.  Set this to one to use
        // the core without flow control.  (A more appropriate name would be
        // the core without flow control.  (A more appropriate name would be
        // the Ready-To-Receive bit ...)
        // the Ready-To-Receive bit ...)
        input                   i_rts;
        input                   i_cts_n;
        // And the UART input line itself
        // And the UART input line itself
        output  reg             o_uart_tx;
        output  reg             o_uart_tx;
        // A line to tell others when we are ready to accept data.  If
        // A line to tell others when we are ready to accept data.  If
        // (i_wr)&&(!o_busy) is ever true, then the core has accepted a byte
        // (i_wr)&&(!o_busy) is ever true, then the core has accepted a byte
        // for transmission.
        // for transmission.
Line 154... Line 154...
        // First step ... handle any hardware flow control, if so enabled.
        // First step ... handle any hardware flow control, if so enabled.
        //
        //
        // Clock in the flow control data, two clocks to avoid metastability
        // Clock in the flow control data, two clocks to avoid metastability
        // Default to using hardware flow control (uart_setup[30]==0 to use it).
        // Default to using hardware flow control (uart_setup[30]==0 to use it).
        // Set this high order bit off if you do not wish to use it.
        // Set this high order bit off if you do not wish to use it.
        reg     q_rts, qq_rts, ck_rts;
        reg     q_cts_n, qq_cts_n, ck_cts;
        // While we might wish to give initial values to q_rts and ck_rts,
        // While we might wish to give initial values to q_rts and ck_cts,
        // 1) it's not required since the transmitter starts in a long wait
        // 1) it's not required since the transmitter starts in a long wait
        // state, and 2) doing so will prevent the synthesizer from optimizing
        // state, and 2) doing so will prevent the synthesizer from optimizing
        // this pin in the case it is hard set to 1'b1 external to this
        // this pin in the case it is hard set to 1'b1 external to this
        // peripheral.
        // peripheral.
        //
        //
        // initial      q_rts  = 1'b0;
        // initial      q_cts_n  = 1'b1;
        // initial      qq_rts  = 1'b0;
        // initial      qq_cts_n = 1'b1;
        // initial      ck_rts = 1'b0;
        // initial      ck_cts   = 1'b0;
        always  @(posedge i_clk)
        always  @(posedge i_clk)
                q_rts <= i_rts;
                q_cts_n <= i_cts_n;
        always  @(posedge i_clk)
        always  @(posedge i_clk)
                qq_rts <= q_rts;
                qq_cts_n <= q_cts_n;
        always  @(posedge i_clk)
        always  @(posedge i_clk)
                ck_rts <= (qq_rts)||(!hw_flow_control);
                ck_cts <= (!qq_cts_n)||(!hw_flow_control);
 
 
        initial o_uart_tx = 1'b1;
        initial o_uart_tx = 1'b1;
        initial r_busy = 1'b1;
        initial r_busy = 1'b1;
        initial state  = `TXU_IDLE;
        initial state  = `TXU_IDLE;
        initial lcl_data= 8'h0;
        initial lcl_data= 8'h0;
Line 206... Line 206...
                                2'b01: state <= `TXU_BIT_ONE;
                                2'b01: state <= `TXU_BIT_ONE;
                                2'b10: state <= `TXU_BIT_TWO;
                                2'b10: state <= `TXU_BIT_TWO;
                                2'b11: state <= `TXU_BIT_THREE;
                                2'b11: state <= `TXU_BIT_THREE;
                                endcase
                                endcase
                        end else begin // Stay in idle
                        end else begin // Stay in idle
                                r_busy <= !ck_rts;
                                r_busy <= !ck_cts;
                        end
                        end
                end else begin
                end else begin
                        // One clock tick in each of these states ...
                        // One clock tick in each of these states ...
                        // baud_counter <= clocks_per_baud - 28'h01;
                        // baud_counter <= clocks_per_baud - 28'h01;
                        r_busy <= 1'b1;
                        r_busy <= 1'b1;

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