Line 47... |
Line 47... |
//
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//
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//
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//
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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//
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//
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`define TXU_BIT_ZERO 4'h0
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`default_nettype none
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`define TXU_BIT_ONE 4'h1
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//
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`define TXU_BIT_TWO 4'h2
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`define TXUL_BIT_ZERO 4'h0
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`define TXU_BIT_THREE 4'h3
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`define TXUL_BIT_ONE 4'h1
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`define TXU_BIT_FOUR 4'h4
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`define TXUL_BIT_TWO 4'h2
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`define TXU_BIT_FIVE 4'h5
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`define TXUL_BIT_THREE 4'h3
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`define TXU_BIT_SIX 4'h6
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`define TXUL_BIT_FOUR 4'h4
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`define TXU_BIT_SEVEN 4'h7
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`define TXUL_BIT_FIVE 4'h5
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`define TXU_STOP 4'h8
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`define TXUL_BIT_SIX 4'h6
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`define TXU_IDLE 4'hf
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`define TXUL_BIT_SEVEN 4'h7
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`define TXUL_STOP 4'h8
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`define TXUL_IDLE 4'hf
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//
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//
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//
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//
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module txuartlite(i_clk, i_wr, i_data, o_uart_tx, o_busy);
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module txuartlite(i_clk, i_wr, i_data, o_uart_tx, o_busy);
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parameter [23:0] CLOCKS_PER_BAUD = 24'd868;
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parameter [23:0] CLOCKS_PER_BAUD = 24'd868;
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input i_clk;
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input wire i_clk;
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input i_wr;
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input wire i_wr;
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input [7:0] i_data;
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input wire [7:0] i_data;
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// And the UART input line itself
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// And the UART input line itself
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output reg o_uart_tx;
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output reg o_uart_tx;
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// A line to tell others when we are ready to accept data. If
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// A line to tell others when we are ready to accept data. If
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// (i_wr)&&(!o_busy) is ever true, then the core has accepted a byte
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// (i_wr)&&(!o_busy) is ever true, then the core has accepted a byte
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// for transmission.
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// for transmission.
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Line 79... |
reg [3:0] state;
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reg [3:0] state;
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reg [7:0] lcl_data;
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reg [7:0] lcl_data;
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reg r_busy, zero_baud_counter;
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reg r_busy, zero_baud_counter;
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initial r_busy = 1'b1;
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initial r_busy = 1'b1;
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initial state = `TXU_IDLE;
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initial state = `TXUL_IDLE;
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initial lcl_data= 8'h0;
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initial lcl_data= 8'h0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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begin
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begin
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if (!zero_baud_counter)
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if (!zero_baud_counter)
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// r_busy needs to be set coming into here
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// r_busy needs to be set coming into here
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r_busy <= 1'b1;
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r_busy <= 1'b1;
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else if (state == `TXU_IDLE) // STATE_IDLE
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else if (state == `TXUL_IDLE) // STATE_IDLE
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begin
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begin
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r_busy <= 1'b0;
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r_busy <= 1'b0;
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if ((i_wr)&&(!r_busy))
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if ((i_wr)&&(!r_busy))
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begin // Immediately start us off with a start bit
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begin // Immediately start us off with a start bit
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r_busy <= 1'b1;
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r_busy <= 1'b1;
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state <= `TXU_BIT_ZERO;
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state <= `TXUL_BIT_ZERO;
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end
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end
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end else begin
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end else begin
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// One clock tick in each of these states ...
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// One clock tick in each of these states ...
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r_busy <= 1'b1;
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r_busy <= 1'b1;
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if (state <=`TXU_STOP) // start bit, 8-d bits, stop-b
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if (state <=`TXUL_STOP) // start bit, 8-d bits, stop-b
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state <= state + 1;
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state <= state + 1;
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else
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else
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state <= `TXU_IDLE;
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state <= `TXUL_IDLE;
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end
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end
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end
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end
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// o_busy
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// o_busy
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//
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//
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Line 175... |
// 3. In the idle state, we stop our counter--so that upon a request
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// 3. In the idle state, we stop our counter--so that upon a request
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// to transmit when idle we can start transmitting immediately, rather
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// to transmit when idle we can start transmitting immediately, rather
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// than waiting for the end of the next (fictitious and arbitrary) baud
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// than waiting for the end of the next (fictitious and arbitrary) baud
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// interval.
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// interval.
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//
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//
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// When (i_wr)&&(!r_busy)&&(state == `TXU_IDLE) then we're not only in
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// When (i_wr)&&(!r_busy)&&(state == `TXUL_IDLE) then we're not only in
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// the idle state, but we also just accepted a command to start writing
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// the idle state, but we also just accepted a command to start writing
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// the next word. At this point, the baud counter needs to be reset
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// the next word. At this point, the baud counter needs to be reset
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// to the number of CLOCKS_PER_BAUD, and zero_baud_counter set to zero.
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// to the number of CLOCKS_PER_BAUD, and zero_baud_counter set to zero.
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//
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//
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// The logic is a bit twisted here, in that it will only check for the
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// The logic is a bit twisted here, in that it will only check for the
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Line 186... |
Line 188... |
initial zero_baud_counter = 1'b0;
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initial zero_baud_counter = 1'b0;
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initial baud_counter = 24'h05;
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initial baud_counter = 24'h05;
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always @(posedge i_clk)
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always @(posedge i_clk)
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begin
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begin
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zero_baud_counter <= (baud_counter == 24'h01);
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zero_baud_counter <= (baud_counter == 24'h01);
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if (state == `TXU_IDLE)
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if (state == `TXUL_IDLE)
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begin
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begin
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baud_counter <= 24'h0;
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baud_counter <= 24'h0;
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zero_baud_counter <= 1'b1;
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zero_baud_counter <= 1'b1;
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if ((i_wr)&&(!r_busy))
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if ((i_wr)&&(!r_busy))
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begin
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begin
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