| Line 45... |
Line 45... |
module wbuart(i_clk, i_rst,
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module wbuart(i_clk, i_rst,
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//
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//
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i_wb_cyc, i_wb_stb, i_wb_we, i_wb_addr, i_wb_data,
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i_wb_cyc, i_wb_stb, i_wb_we, i_wb_addr, i_wb_data,
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o_wb_ack, o_wb_stall, o_wb_data,
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o_wb_ack, o_wb_stall, o_wb_data,
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//
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//
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i_uart_rx, o_uart_tx, i_rts, o_cts,
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i_uart_rx, o_uart_tx, i_cts_n, o_rts_n,
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// i_uart_rts, o_uart_cts, i_uart_dtr, o_uart_dts
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//
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//
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o_uart_rx_int, o_uart_tx_int,
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o_uart_rx_int, o_uart_tx_int,
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o_uart_rxfifo_int, o_uart_txfifo_int);
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o_uart_rxfifo_int, o_uart_txfifo_int);
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parameter [30:0] INITIAL_SETUP = 31'd25; // 4MB 8N1, when using 100MHz clock
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parameter [30:0] INITIAL_SETUP = 31'd25; // 4MB 8N1, when using 100MHz clock
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parameter [3:0] LGFLEN = 4;
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parameter [3:0] LGFLEN = 4;
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| Line 75... |
Line 74... |
// RTS is used for hardware flow control. According to Wikipedia, it
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// RTS is used for hardware flow control. According to Wikipedia, it
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// should probably be renamed RTR for "ready to receive". It tell us
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// should probably be renamed RTR for "ready to receive". It tell us
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// whether or not the receiving hardware is ready to accept another
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// whether or not the receiving hardware is ready to accept another
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// byte. If low, the transmitter will pause.
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// byte. If low, the transmitter will pause.
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//
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//
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// If you don't wish to use hardware flow control, just set i_rts to
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// If you don't wish to use hardware flow control, just set i_cts_n to
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// 1'b1 and let the optimizer simply remove this logic.
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// 1'b0 and let the optimizer simply remove this logic.
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input i_rts;
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input i_cts_n;
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// CTS is the "Clear-to-send" signal. We set it anytime our FIFO
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// CTS is the "Clear-to-send" signal. We set it anytime our FIFO
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// isn't full. Feel free to ignore this output if you do not wish to
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// isn't full. Feel free to ignore this output if you do not wish to
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// use flow control.
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// use flow control.
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output reg o_cts;
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output reg o_rts_n;
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output wire o_uart_rx_int, o_uart_tx_int,
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output wire o_uart_rx_int, o_uart_tx_int,
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o_uart_rxfifo_int, o_uart_txfifo_int;
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o_uart_rxfifo_int, o_uart_txfifo_int;
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wire tx_busy;
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wire tx_busy;
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Line 117... |
wire [7:0] rx_uart_data;
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wire [7:0] rx_uart_data;
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reg rx_uart_reset;
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reg rx_uart_reset;
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// Here's our UART receiver. Basically, it accepts our setup wires,
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// Here's our UART receiver. Basically, it accepts our setup wires,
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// the UART input, a clock, and a reset line, and produces outputs:
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// the UART input, a clock, and a reset line, and produces outputs:
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// a stb (true when new data is ready), an 8-bit data out value
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// a stb (true when new data is ready), and an 8-bit data out value
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// valid when stb is high, a break value (true during a break cond.),
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// valid when stb is high.
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// and parity/framing error flags--also valid when stb is true.
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`ifdef USE_LITE_UART
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rxuartlite #(INITIAL_SETUP[23:0])
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rx(i_clk, (i_rst), i_uart_rx, rx_stb, rx_uart_data);
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assign rx_break = 1'b0;
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assign rx_perr = 1'b0;
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assign rx_ferr = 1'b0;
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assign ck_uart = 1'b0;
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`else
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// The full receiver also produces a break value (true during a break
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// cond.), and parity/framing error flags--also valid when stb is true.
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rxuart #(INITIAL_SETUP) rx(i_clk, (i_rst)||(rx_uart_reset),
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rxuart #(INITIAL_SETUP) rx(i_clk, (i_rst)||(rx_uart_reset),
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uart_setup, i_uart_rx,
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uart_setup, i_uart_rx,
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rx_stb, rx_uart_data, rx_break,
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rx_stb, rx_uart_data, rx_break,
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rx_perr, rx_ferr, ck_uart);
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rx_perr, rx_ferr, ck_uart);
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// The real trick is ... now that we have this data, what do we do
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// The real trick is ... now that we have this extra data, what do we do
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// with it?
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// with it?
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`endif
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// We place it into a receiver FIFO.
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// We place it into a receiver FIFO.
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//
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//
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// Here's the declarations for the wires it needs.
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// Here's the declarations for the wires it needs.
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Line 177... |
// to be true any time the FIFO has fewer than N-2 items in it.
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// to be true any time the FIFO has fewer than N-2 items in it.
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// Why N-1? Because at N-1 we are totally full, but already so full
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// Why N-1? Because at N-1 we are totally full, but already so full
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// that if the transmit end starts sending we won't have a location to
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// that if the transmit end starts sending we won't have a location to
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// receive it. (Transmit might've started on the next character by the
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// receive it. (Transmit might've started on the next character by the
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// time we set this--need to set it to one character before necessary
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// time we set this--need to set it to one character before necessary
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// thus.)
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wire [(LCLLGFLEN-1):0] check_cutoff;
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assign check_cutoff = -3;
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always @(posedge i_clk)
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always @(posedge i_clk)
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o_cts = (!HARDWARE_FLOW_CONTROL_PRESENT)
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o_rts_n = ((HARDWARE_FLOW_CONTROL_PRESENT)
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||(rxf_status[(LCLLGFLEN+1):2] > check_cutoff);
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&&(!uart_setup[30])
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&&(rxf_status[(LCLLGFLEN+1):4]=={(LCLLGFLEN-2){1'b1}}));
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// If the bus requests that we read from the receive FIFO, we need to
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// If the bus requests that we read from the receive FIFO, we need to
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// tell this to the receive FIFO. Note that because we are using a
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// tell this to the receive FIFO. Note that because we are using a
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// clock here, the output from the receive FIFO will necessarily be
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// clock here, the output from the receive FIFO will necessarily be
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// delayed by an extra clock.
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// delayed by an extra clock.
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Line 255... |
//
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//
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// Then the UART transmitter
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// Then the UART transmitter
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//
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//
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//
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//
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/////////////////////////////////////////
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/////////////////////////////////////////
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wire tx_empty_n, txf_err;
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wire tx_empty_n, txf_err, tx_break;
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wire [7:0] tx_data;
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wire [7:0] tx_data;
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wire [15:0] txf_status;
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wire [15:0] txf_status;
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reg r_tx_break, txf_wb_write, tx_uart_reset;
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reg txf_wb_write, tx_uart_reset;
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reg [7:0] txf_wb_data;
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reg [7:0] txf_wb_data;
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// Unlike the receiver which goes from RXUART -> UFIFO -> WB, the
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// Unlike the receiver which goes from RXUART -> UFIFO -> WB, the
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// transmitter basically goes WB -> UFIFO -> TXUART. Hence, to build
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// transmitter basically goes WB -> UFIFO -> TXUART. Hence, to build
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// support for the transmitter, we start with the command to write data
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// support for the transmitter, we start with the command to write data
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Line 287... |
// differences to note: we reset the transmitter on any request for a
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// differences to note: we reset the transmitter on any request for a
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// break. We read from the FIFO any time the UART transmitter is idle.
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// break. We read from the FIFO any time the UART transmitter is idle.
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// and ... we just set the values (above) for controlling writing into
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// and ... we just set the values (above) for controlling writing into
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// this.
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// this.
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ufifo #(.LGFLEN(LGFLEN), .RXFIFO(0))
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ufifo #(.LGFLEN(LGFLEN), .RXFIFO(0))
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txfifo(i_clk, (r_tx_break)||(tx_uart_reset),
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txfifo(i_clk, (tx_break)||(tx_uart_reset),
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txf_wb_write, txf_wb_data,
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txf_wb_write, txf_wb_data,
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tx_empty_n,
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tx_empty_n,
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(!tx_busy)&&(tx_empty_n), tx_data,
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(!tx_busy)&&(tx_empty_n), tx_data,
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txf_status, txf_err);
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txf_status, txf_err);
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// Let's create two transmit based interrupts from the FIFO for the CPU.
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// Let's create two transmit based interrupts from the FIFO for the CPU.
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| Line 294... |
Line 301... |
// The second will be true any time the FIFO is less than half
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// The second will be true any time the FIFO is less than half
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// full, allowing us a change to always keep it (near) fully
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// full, allowing us a change to always keep it (near) fully
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// charged.
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// charged.
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assign o_uart_txfifo_int = txf_status[1];
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assign o_uart_txfifo_int = txf_status[1];
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`ifndef USE_LITE_UART
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// Break logic
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// Break logic
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//
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//
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// A break in a UART controller is any time the UART holds the line
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// A break in a UART controller is any time the UART holds the line
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// low for an extended period of time. Here, we capture the wb_data[9]
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// low for an extended period of time. Here, we capture the wb_data[9]
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// wire, on writes, as an indication we wish to break. As long as you
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// wire, on writes, as an indication we wish to break. As long as you
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// write unsigned characters to the interface, this will never be true
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// write unsigned characters to the interface, this will never be true
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// unless you wish it to be true. Be aware, though, writing a valid
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// unless you wish it to be true. Be aware, though, writing a valid
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// value to the interface will bring it out of the break condition.
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// value to the interface will bring it out of the break condition.
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reg r_tx_break;
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initial r_tx_break = 1'b0;
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initial r_tx_break = 1'b0;
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always @(posedge i_clk)
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always @(posedge i_clk)
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if (i_rst)
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if (i_rst)
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r_tx_break <= 1'b0;
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r_tx_break <= 1'b0;
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else if ((i_wb_stb)&&(i_wb_addr[1:0]==`UART_TXREG)&&(i_wb_we))
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else if ((i_wb_stb)&&(i_wb_addr[1:0]==`UART_TXREG)&&(i_wb_we))
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r_tx_break <= i_wb_data[9];
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r_tx_break <= i_wb_data[9];
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assign tx_break = r_tx_break;
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`else
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assign tx_break = 1'b0;
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`endif
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// TX-Reset logic
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// TX-Reset logic
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//
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//
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// This is nearly identical to the RX reset logic above. Basically,
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// This is nearly identical to the RX reset logic above. Basically,
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// any time someone writes to bit [12] the transmitter will go through
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// any time someone writes to bit [12] the transmitter will go through
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| Line 324... |
Line 337... |
else if ((i_wb_stb)&&(i_wb_addr[1:0]==`UART_TXREG)&&(i_wb_we))
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else if ((i_wb_stb)&&(i_wb_addr[1:0]==`UART_TXREG)&&(i_wb_we))
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tx_uart_reset <= i_wb_data[12];
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tx_uart_reset <= i_wb_data[12];
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else
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else
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tx_uart_reset <= 1'b0;
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tx_uart_reset <= 1'b0;
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wire rts;
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`ifdef USE_LITE_UART
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assign rts = (!HARDWARE_FLOW_CONTROL_PRESENT)||(i_rts);
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txuart #(INITIAL_SETUP[23:0]) tx(i_clk, (tx_empty_n), tx_data,
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o_uart_tx, tx_busy);
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`else
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wire cts_n;
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assign cts_n = (HARDWARE_FLOW_CONTROL_PRESENT)&&(i_cts_n);
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// Finally, the UART transmitter module itself. Note that we haven't
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// Finally, the UART transmitter module itself. Note that we haven't
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// connected the reset wire. Transmitting is as simple as setting
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// connected the reset wire. Transmitting is as simple as setting
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// the stb value (here set to tx_empty_n) and the data. When these
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// the stb value (here set to tx_empty_n) and the data. When these
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// are both set on the same clock that tx_busy is low, the transmitter
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// are both set on the same clock that tx_busy is low, the transmitter
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// will move on to the next data byte. Really, the only thing magical
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// will move on to the next data byte. Really, the only thing magical
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| Line 337... |
Line 354... |
// we read it here. (You might notice above, we register a read any
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// we read it here. (You might notice above, we register a read any
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// time (tx_empty_n) and (!tx_busy) are both true---the condition for
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// time (tx_empty_n) and (!tx_busy) are both true---the condition for
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// starting to transmit a new byte.)
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// starting to transmit a new byte.)
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txuart #(INITIAL_SETUP) tx(i_clk, 1'b0, uart_setup,
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txuart #(INITIAL_SETUP) tx(i_clk, 1'b0, uart_setup,
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r_tx_break, (tx_empty_n), tx_data,
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r_tx_break, (tx_empty_n), tx_data,
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i_rts, o_uart_tx, tx_busy);
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cts_n, o_uart_tx, tx_busy);
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`endif
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// Now that we are done with the chain, pick some wires for the user
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// Now that we are done with the chain, pick some wires for the user
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// to read on any read of the transmit port.
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// to read on any read of the transmit port.
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//
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//
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// This port is different from reading from the receive port, since
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// This port is different from reading from the receive port, since
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| Line 353... |
Line 371... |
// voltage on the line (o_uart_tx)--and even the voltage on the receive
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// voltage on the line (o_uart_tx)--and even the voltage on the receive
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// line (ck_uart), as well as our current setting of the break and
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// line (ck_uart), as well as our current setting of the break and
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// whether or not we are actively transmitting.
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// whether or not we are actively transmitting.
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wire [31:0] wb_tx_data;
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wire [31:0] wb_tx_data;
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assign wb_tx_data = { 16'h00,
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assign wb_tx_data = { 16'h00,
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i_rts, txf_status[1:0], txf_err,
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i_cts_n, txf_status[1:0], txf_err,
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ck_uart, o_uart_tx, r_tx_break, (tx_busy|txf_status[0]),
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ck_uart, o_uart_tx, tx_break, (tx_busy|txf_status[0]),
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(tx_busy|txf_status[0])?txf_wb_data:8'b00};
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(tx_busy|txf_status[0])?txf_wb_data:8'b00};
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// Each of the FIFO's returns a 16 bit status value. This value tells
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// Each of the FIFO's returns a 16 bit status value. This value tells
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// us both how big the FIFO is, as well as how much of the FIFO is in
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// us both how big the FIFO is, as well as how much of the FIFO is in
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// use. Let's merge those two status words together into a word we
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// use. Let's merge those two status words together into a word we
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