URL
https://opencores.org/ocsvn/wdsp/wdsp/trunk
[/] [wdsp/] [trunk/] [sw/] [IIR6/] [IIR6.c] - Diff between revs 5 and 11
Show entire file |
Details |
Blame |
View Log
| Rev 5 |
Rev 11 |
| Line 125... |
Line 125... |
|
|
//Coef Write
|
//Coef Write
|
for (k=0;k<(6*NSECT);k++){
|
for (k=0;k<(6*NSECT);k++){
|
REG32(IIR_BASE+IIR_COEFF+(k*4))=(int)SOS[k];
|
REG32(IIR_BASE+IIR_COEFF+(k*4))=(int)SOS[k];
|
r_out=REG32(IIR_BASE+IIR_COEFF+(k*4));
|
r_out=REG32(IIR_BASE+IIR_COEFF+(k*4));
|
|
int10_to_str(r_out,str,-10);
|
|
uart_print_str(str);
|
|
uart_putc(' ');
|
|
|
|
|
}
|
}
|
|
|
uart_print_str("IIR filter impulse response :\n ");
|
uart_print_str("IIR filter impulse response :\n ");
|
|
|
| Line 138... |
Line 142... |
REG32(IIR_BASE+IIR_CONTROL)=1;//Start
|
REG32(IIR_BASE+IIR_CONTROL)=1;//Start
|
while(REG32(IIR_BASE+IIR_STATUS)==0) ;
|
while(REG32(IIR_BASE+IIR_STATUS)==0) ;
|
REG32(IIR_BASE+IIR_STATUS)=1;
|
REG32(IIR_BASE+IIR_STATUS)=1;
|
|
|
|
|
//Waits for filtering
|
|
while(REG32(IIR_BASE+IIR_STATUS)==0) ;
|
|
REG32(IIR_BASE+IIR_STATUS)=1;
|
|
|
|
//Reads filter output
|
//Reads filter output
|
r_out=REG32(IIR_BASE+IIR_DATA);
|
r_out=REG32(IIR_BASE+IIR_DATA);
|
int10_to_str(r_out,str,-10);
|
int10_to_str(r_out,str,-10);
|
uart_print_str(str);
|
uart_print_str(str);
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.