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//
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//
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// Abstract:
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// Abstract:
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// Asynchronus FIFO
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// Asynchronus FIFO
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//
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//
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// Author:
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// Author:
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// Kenji Ishimaru (kenji.ishimaru@prtissimo.com)
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// Kenji Ishimaru (info.wf3d@gmail.com)
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//
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//
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//======================================================================
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//======================================================================
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//
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//
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// Copyright (c) 2015, Kenji Ishimaru
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// Copyright (c) 2015, Kenji Ishimaru
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// All rights reserved.
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// All rights reserved.
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| Line 54... |
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);
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);
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// set default parameters
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// set default parameters
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parameter P_RANGE = 7;
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parameter P_RANGE = 7;
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parameter P_DEPTH = 1 << P_RANGE; // 128
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parameter P_DEPTH = 1 << P_RANGE; // 128
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`ifdef PP_BUSWIDTH_64
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localparam P_IB_DATA_WIDTH = 'd64;
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`else
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localparam P_IB_DATA_WIDTH = 'd32;
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`endif
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////////////////////////////
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////////////////////////////
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// I/O definition
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// I/O definition
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////////////////////////////
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////////////////////////////
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input clk_core; // system clock
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input clk_core; // system clock
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input clk_vi;
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input clk_vi;
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input rst_x; // system reset
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input rst_x; // system reset
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input [1:0] i_color_mode;
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input [1:0] i_color_mode;
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input i_wstrobe; // write strobe
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input i_wstrobe; // write strobe
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input [31:0] i_dt; // write data
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input [P_IB_DATA_WIDTH-1:0]
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i_dt; // write data
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output o_full; // write data full
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output o_full; // write data full
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input i_renable; // read enable
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input i_renable; // read enable
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output [15:0] o_dt; // read data
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output [15:0] o_dt; // read data
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output o_empty; // read data empty
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output o_empty; // read data empty
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output [P_RANGE:0] o_dnum; // written data number
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output [P_RANGE:0] o_dnum; // written data number
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// Register definition
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// Register definition
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/////////////////////////
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/////////////////////////
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reg [P_RANGE-1:0] r_write_counter;
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reg [P_RANGE-1:0] r_write_counter;
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reg [P_RANGE-1:0] r_read_counter;
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reg [P_RANGE-1:0] r_read_counter;
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// data registers
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// data registers
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`ifdef PP_BUSWIDTH_64
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reg [3:0] r_select_hw;
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`else
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reg [2:0] r_select_hw;
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reg [2:0] r_select_hw;
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`endif
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/////////////////////////
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/////////////////////////
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// wire definition
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// wire definition
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/////////////////////////
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/////////////////////////
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wire o_full;
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wire o_full;
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wire o_empty;
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wire o_empty;
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wire [15:0] o_dt;
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wire [15:0] o_dt;
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wire w_we;
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wire w_we;
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wire w_re;
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wire w_re;
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wire [31:0] w_dt32;
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wire [P_IB_DATA_WIDTH-1:0]
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w_dt;
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wire [P_RANGE-1:0] w_read_counter_inc;
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wire [P_RANGE-1:0] w_read_counter_inc;
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wire [P_RANGE-1:0] w_read_counter;
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wire [P_RANGE-1:0] w_read_counter;
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wire [15:0] w_dt16;
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wire [15:0] w_dt16;
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wire [7:0] w_dt8;
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wire [7:0] w_dt8;
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wire [3:0] w_dt4;
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wire [3:0] w_dt4;
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// /////////////////////////
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// /////////////////////////
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// assign statement
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// assign statement
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/////////////////////////
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/////////////////////////
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assign w_dt16 = (r_select_hw[0]) ? w_dt32[31:16] : w_dt32[15:0];
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`ifdef PP_BUSWIDTH_64
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assign w_dt8 = (r_select_hw[1:0] == 'd3) ? w_dt32[31:24] :
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assign w_dt16 = (r_select_hw[1:0] == 'd3) ? w_dt[63:48] :
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(r_select_hw[1:0] == 'd2) ? w_dt32[23:16] :
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(r_select_hw[1:0] == 'd2) ? w_dt[47:32] :
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(r_select_hw[1:0] == 'd1) ? w_dt32[15:8] :
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(r_select_hw[1:0] == 'd1) ? w_dt[31:16] :
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w_dt32[7:0];
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w_dt[15:0];
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assign w_dt4 = (r_select_hw[2:0] == 'd7) ? w_dt32[31:28] :
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assign w_dt8 = (r_select_hw[2:0] == 'd7) ? w_dt[63:56] :
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(r_select_hw[2:0] == 'd6) ? w_dt32[27:24] :
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(r_select_hw[2:0] == 'd6) ? w_dt[55:48] :
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(r_select_hw[2:0] == 'd5) ? w_dt32[23:20] :
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(r_select_hw[2:0] == 'd5) ? w_dt[47:40] :
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(r_select_hw[2:0] == 'd4) ? w_dt32[19:16] :
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(r_select_hw[2:0] == 'd4) ? w_dt[39:32] :
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(r_select_hw[2:0] == 'd3) ? w_dt32[15:12] :
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(r_select_hw[2:0] == 'd3) ? w_dt[31:24] :
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(r_select_hw[2:0] == 'd2) ? w_dt32[11:8] :
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(r_select_hw[2:0] == 'd2) ? w_dt[23:16] :
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(r_select_hw[2:0] == 'd1) ? w_dt32[7:4] :
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(r_select_hw[2:0] == 'd1) ? w_dt[15:8] :
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w_dt32[3:0];
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w_dt[7:0];
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assign w_dt4 = (r_select_hw[3:0] == 'd15) ? w_dt[63:60] :
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(r_select_hw[3:0] == 'd14) ? w_dt[59:56] :
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(r_select_hw[3:0] == 'd13) ? w_dt[55:52] :
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(r_select_hw[3:0] == 'd12) ? w_dt[51:48] :
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(r_select_hw[3:0] == 'd11) ? w_dt[47:44] :
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(r_select_hw[3:0] == 'd10) ? w_dt[43:40] :
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(r_select_hw[3:0] == 'd9) ? w_dt[39:36] :
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(r_select_hw[3:0] == 'd8) ? w_dt[35:32] :
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(r_select_hw[3:0] == 'd7) ? w_dt[31:28] :
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(r_select_hw[3:0] == 'd6) ? w_dt[27:24] :
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(r_select_hw[3:0] == 'd5) ? w_dt[23:20] :
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(r_select_hw[3:0] == 'd4) ? w_dt[19:16] :
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(r_select_hw[3:0] == 'd3) ? w_dt[15:12] :
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(r_select_hw[3:0] == 'd2) ? w_dt[11:8] :
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(r_select_hw[3:0] == 'd1) ? w_dt[7:4] :
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w_dt[3:0];
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assign w_re = i_renable & ((i_color_mode == 'd3) ? (r_select_hw[3:0] == 'd15) :
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(i_color_mode == 'd2) ? (r_select_hw[2:0] == 'd7) :
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(r_select_hw[1:0] == 'd3)
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);
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`else
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assign w_dt16 = (r_select_hw[0]) ? w_dt[31:16] : w_dt[15:0];
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assign w_dt8 = (r_select_hw[1:0] == 'd3) ? w_dt[31:24] :
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(r_select_hw[1:0] == 'd2) ? w_dt[23:16] :
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(r_select_hw[1:0] == 'd1) ? w_dt[15:8] :
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w_dt[7:0];
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assign w_dt4 = (r_select_hw[2:0] == 'd7) ? w_dt[31:28] :
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(r_select_hw[2:0] == 'd6) ? w_dt[27:24] :
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(r_select_hw[2:0] == 'd5) ? w_dt[23:20] :
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(r_select_hw[2:0] == 'd4) ? w_dt[19:16] :
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(r_select_hw[2:0] == 'd3) ? w_dt[15:12] :
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(r_select_hw[2:0] == 'd2) ? w_dt[11:8] :
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(r_select_hw[2:0] == 'd1) ? w_dt[7:4] :
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w_dt[3:0];
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assign w_re = i_renable & ((i_color_mode == 'd3) ? (r_select_hw == 'd7) :
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(i_color_mode == 'd2) ? (r_select_hw[1:0] == 'd3) :
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(r_select_hw[0] == 'd1)
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);
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`endif
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assign o_dt = (i_color_mode == 'd3) ? {12'd0,w_dt4} :
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assign o_dt = (i_color_mode == 'd3) ? {12'd0,w_dt4} :
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(i_color_mode == 'd2) ? {8'd0,w_dt8} :
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(i_color_mode == 'd2) ? {8'd0,w_dt8} :
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w_dt16 ;
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w_dt16 ;
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assign o_dnum = 0;
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assign o_dnum = 0;
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assign o_full = 1'b0;
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assign o_full = 1'b0;
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assign o_empty = 1'b0;
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assign o_empty = 1'b0;
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assign w_we = i_wstrobe;
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assign w_we = i_wstrobe;
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assign w_re = i_renable & ((i_color_mode == 'd3) ? (r_select_hw == 'd7) :
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(i_color_mode == 'd2) ? (r_select_hw[1:0] == 'd3) :
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(r_select_hw[0] == 'd1)
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);
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assign w_read_counter_inc = r_read_counter + 1'b1;
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assign w_read_counter_inc = r_read_counter + 1'b1;
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assign w_read_counter = (w_re) ? w_read_counter_inc : r_read_counter;
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assign w_read_counter = (w_re) ? w_read_counter_inc : r_read_counter;
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////////////////////////
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////////////////////////
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// always
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// always
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Line 199... |
end
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end
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// select half word
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// select half word
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always @(posedge clk_vi or negedge rst_x) begin
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always @(posedge clk_vi or negedge rst_x) begin
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if (~rst_x) begin
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if (~rst_x) begin
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r_select_hw <= 3'b0;
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r_select_hw <= 'd0;
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end else begin
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end else begin
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if (i_renable) r_select_hw <= r_select_hw + 1'b1;
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if (i_renable) r_select_hw <= r_select_hw + 1'b1;
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end
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end
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end
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end
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///////////////////
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///////////////////
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// module instance
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// module instance
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///////////////////
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///////////////////
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`ifdef PP_BUSWIDTH_64
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fm_cmn_ram #(.P_RAM_TYPE("TYPE_A"),.P_WIDTH(64),.P_RANGE( P_RANGE)) ram_00 (
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`else
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fm_cmn_ram #(.P_RAM_TYPE("TYPE_A"),.P_WIDTH(32),.P_RANGE( P_RANGE)) ram_00 (
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fm_cmn_ram #(.P_RAM_TYPE("TYPE_A"),.P_WIDTH(32),.P_RANGE( P_RANGE)) ram_00 (
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`endif
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.clka(clk_core),
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.clka(clk_core),
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.clkb(clk_vi),
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.clkb(clk_vi),
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.wea(w_we),
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.wea(w_we),
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.addra(r_write_counter),
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.addra(r_write_counter),
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.addrb(w_read_counter),
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.addrb(w_read_counter),
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.dia(i_dt),
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.dia(i_dt),
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.doa(),
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.doa(),
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.dob(w_dt32)
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.dob(w_dt)
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);
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);
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endmodule
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endmodule
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