| Line 7... |
Line 7... |
//
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//
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// Abstract:
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// Abstract:
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// VGA LCD Controller
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// VGA LCD Controller
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//
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//
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// Author:
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// Author:
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// Kenji Ishimaru (kenji.ishimaru@prtissimo.com)
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// Kenji Ishimaru (info.wf3d@gmail.com)
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//
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//
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//======================================================================
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//======================================================================
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//
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//
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// Copyright (c) 2015, Kenji Ishimaru
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// Copyright (c) 2015, Kenji Ishimaru
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// All rights reserved.
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// All rights reserved.
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Line 36... |
// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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// WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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// OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
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// OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
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// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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//
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// Revision History
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// Revision History
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// 2016/08/14 64-bit bus support
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|
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module fm_hvc (
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module fm_hvc (
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clk_core,
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clk_core,
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clk_vi,
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clk_vi,
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rst_x,
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rst_x,
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// configuration registers
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// configuration registers
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i_video_start,
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i_video_start,
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i_fb0_offset,
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i_fb0_offset,
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i_fb0_ms_offset,
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i_fb1_offset,
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i_fb1_offset,
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i_fb1_ms_offset,
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i_color_mode,
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i_color_mode,
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i_front_buffer,
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i_front_buffer,
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i_aa_en,
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i_fb_blend_en,
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// status out
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// status out
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o_vint_x,
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o_vint_x,
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o_vint_edge,
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o_vint_edge,
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// dram if
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// dram if
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o_req,
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o_req,
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| Line 71... |
Line 68... |
o_vsync_x,
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o_vsync_x,
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o_hsync_x,
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o_hsync_x,
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o_blank_x,
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o_blank_x,
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o_de
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o_de
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);
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);
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localparam P_IB_LEN_WIDTH = 'd6;
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`ifdef PP_BUSWIDTH_64
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localparam P_IB_BASE_WIDTH = 'd12;
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localparam P_IB_ADDR_WIDTH = 'd29;
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localparam P_IB_DATA_WIDTH = 'd64;
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`else
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localparam P_IB_BASE_WIDTH = 'd7;
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localparam P_IB_ADDR_WIDTH = 'd24;
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localparam P_IB_DATA_WIDTH = 'd32;
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`endif
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//////////////////////////////////
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//////////////////////////////////
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// I/O port definition
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// I/O port definition
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//////////////////////////////////
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//////////////////////////////////
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input clk_core;
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input clk_core;
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input clk_vi; // 25MHz
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input clk_vi; // 25MHz
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input rst_x;
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input rst_x;
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// configuration registers
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// configuration registers
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input i_video_start;
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input i_video_start;
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input [6:0] i_fb0_offset;
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input [P_IB_BASE_WIDTH-1:0] i_fb0_offset;
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input [3:0] i_fb0_ms_offset;
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input [P_IB_BASE_WIDTH-1:0] i_fb1_offset;
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input [6:0] i_fb1_offset;
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input [3:0] i_fb1_ms_offset;
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input [1:0] i_color_mode;
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input [1:0] i_color_mode;
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input i_front_buffer;
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input i_front_buffer;
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input [2:0] i_aa_en;
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input i_fb_blend_en;
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// status out
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// status out
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output o_vint_x;
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output o_vint_x;
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output o_vint_edge;
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output o_vint_edge;
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// dram if
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// dram if
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output o_req;
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output o_req;
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output [23:0] o_adrs;
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output [P_IB_ADDR_WIDTH-1:0]
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output [5:0] o_len;
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o_adrs;
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output [P_IB_LEN_WIDTH-1:0]
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o_len;
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input i_ack;
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input i_ack;
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input i_rstr;
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input i_rstr;
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input [31:0] i_rd;
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input [P_IB_DATA_WIDTH-1:0]
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i_rd;
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output clk_vo;
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output clk_vo;
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output [7:0] o_r;
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output [7:0] o_r;
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output [7:0] o_g;
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output [7:0] o_g;
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output [7:0] o_b;
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output [7:0] o_b;
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Line 154... |
.o_hsync_x(o_hsync_x),
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.o_hsync_x(o_hsync_x),
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.o_blank_x(o_blank_x),
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.o_blank_x(o_blank_x),
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.o_de(o_de)
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.o_de(o_de)
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);
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);
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fm_hvc_dma fm_hvc_dma (
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`ifdef PP_USE_AXI
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`ifdef PP_BUSWIDTH_64
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`else
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wire w_req;
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wire [P_IB_ADDR_WIDTH-1:0]
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w_adrs;
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wire [P_IB_LEN_WIDTH-1:0]
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w_len;
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wire w_ack;
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fm_rd_split fm_rd_split (
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.clk_core(clk_core),
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.rst_x(rst_x),
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.i_req(w_req),
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.i_adrs(w_adrs),
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.i_len(w_len),
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.o_ack(w_ack),
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// dram if
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.o_req(o_req),
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.o_adrs(o_adrs),
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.o_len(o_len),
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.i_ack(i_ack)
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);
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`endif
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`endif
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fm_hvc_dma #(.P_IB_ADDR_WIDTH(P_IB_ADDR_WIDTH),
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.P_IB_LEN_WIDTH(P_IB_LEN_WIDTH))
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fm_hvc_dma (
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.clk_core(clk_core),
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.clk_core(clk_core),
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.rst_x(rst_x),
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.rst_x(rst_x),
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.i_color_mode(i_color_mode),
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.i_color_mode(i_color_mode),
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.i_video_start(i_video_start),
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.i_video_start(i_video_start),
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.i_vsync(w_vsync_i),
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.i_vsync(w_vsync_i),
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.i_hsync(w_hsync_i),
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.i_hsync(w_hsync_i),
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.i_fb0_offset(i_fb0_offset),
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.i_fb0_offset(i_fb0_offset),
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.i_fb0_ms_offset(i_fb0_ms_offset),
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.i_fb1_offset(i_fb1_offset),
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.i_fb1_offset(i_fb1_offset),
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.i_fb1_ms_offset(i_fb1_ms_offset),
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.i_front_buffer(i_front_buffer),
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.i_front_buffer(i_front_buffer),
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.i_aa_en(i_aa_en[0]),
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.i_fifo_available(w_fifo_available),
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.i_fifo_available(w_fifo_available),
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.o_fifo_available_ack(w_fifo_available_ack),
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.o_fifo_available_ack(w_fifo_available_ack),
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.o_vsync(o_vint_x),
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.o_vsync(o_vint_x),
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.o_vsync_edge(o_vint_edge),
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.o_vsync_edge(o_vint_edge),
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// dram if
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// dram if
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`ifdef PP_USE_AXI
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`ifdef PP_BUSWIDTH_64
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.o_req(o_req),
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.o_adrs(o_adrs),
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.o_len(o_len),
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.i_ack(i_ack)
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`else
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.o_req(w_req),
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.o_adrs(w_adrs),
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.o_len(w_len),
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.i_ack(w_ack)
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`endif
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`else
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.o_req(o_req),
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.o_req(o_req),
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.o_adrs(o_adrs),
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.o_adrs(o_adrs),
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.o_len(o_len),
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.o_len(o_len),
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.i_ack(i_ack)
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.i_ack(i_ack)
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`endif
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);
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);
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fm_hvc_data fm_hvc_data (
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fm_hvc_data fm_hvc_data (
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.clk_core(clk_core),
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.clk_core(clk_core),
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.clk_vi(clk_vi),
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.clk_vi(clk_vi),
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