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https://opencores.org/ocsvn/wishbone_bfm/wishbone_bfm/trunk
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CYCLE_IS : OUT cycle_type
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CYCLE_IS : OUT cycle_type
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);
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);
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END COMPONENT;
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END COMPONENT;
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-- Component Declaration for wishbone slave
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COMPONENT wb_mem_32x16
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PORT(
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ACK_O : out std_logic;
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ADR_I : in std_logic_vector( 3 downto 0 );
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CLK_I : in std_logic;
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DAT_I : in std_logic_vector( 31 downto 0 );
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DAT_O : out std_logic_vector( 31 downto 0 );
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STB_I : in std_logic;
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WE_I : in std_logic
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);
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END COMPONENT;
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--Inputs
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--Inputs
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SIGNAL RST_I : std_logic := '0';
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SIGNAL RST_I : std_logic := '0';
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SIGNAL CLK_I : std_logic := '0';
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SIGNAL CLK_I : std_logic := '0';
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SIGNAL ACK_I : std_logic := '0';
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SIGNAL ACK_I : std_logic := '0';
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SIGNAL ERR_I : std_logic := '0';
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SIGNAL ERR_I : std_logic := '0';
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-- ---------------------------------------------------------------
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-- ---------------------------------------------------------------
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BEGIN
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BEGIN
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-- ---------------------------------------------------------------
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-- ---------------------------------------------------------------
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-- module port => signal name
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-- Instantiate the system controler
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-- Instantiate the system controler
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sys_con: syscon PORT MAP(
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sys_con: syscon PORT MAP(
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RST_sys => RST_sys,
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RST_sys => RST_sys,
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CLK_stop => CLK_stop,
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CLK_stop => CLK_stop,
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RST_O => RST_I,
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RST_O => RST_I,
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LOCK_O => LOCK_O,
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LOCK_O => LOCK_O,
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SEL_O => SEL_O,
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SEL_O => SEL_O,
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CYCLE_IS => CYCLE_IS
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CYCLE_IS => CYCLE_IS
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);
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);
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ACK_I <= STB_O; -- temp wire strobe to ack
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-- Instantiate the wishbone slave
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wb_s1: wb_mem_32x16 PORT MAP(
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ACK_O => ACK_I,
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ADR_I => ADR_O( 3 downto 0 ),
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CLK_I => CLK_I,
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DAT_I => DAT_O,
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DAT_O => DAT_I,
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STB_I => STB_O,
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WE_I => WE_O
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);
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END;
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END;
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