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https://opencores.org/ocsvn/wishbone_bfm/wishbone_bfm/trunk
[/] [wishbone_bfm/] [trunk/] [rtl/] [wb_master.vhd] - Diff between revs 8 and 10
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-------------------------------------------------------------------------------
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-------------------------------------------------------------------------------
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---- ----
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---- ----
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---- WISHBONE XXX IP Core ----
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---- WISHBONE Wishbone_BFM IP Core ----
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---- ----
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---- ----
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---- This file is part of the XXX project ----
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---- This file is part of the Wishbone_BFM project ----
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---- http://www.opencores.org/cores/xxx/ ----
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---- http://www.opencores.org/cores/Wishbone_BFM/ ----
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---- ----
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---- ----
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---- Description ----
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---- Description ----
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---- Implementation of XXX IP core according to ----
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---- Implementation of Wishbone_BFM IP core according to ----
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---- XXX IP core specification document. ----
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---- Wishbone_BFM IP core specification document. ----
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---- ----
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---- ----
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---- To Do: ----
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---- To Do: ----
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---- NA ----
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---- NA ----
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---- ----
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---- ----
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---- Author(s): ----
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---- Author(s): ----
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wr_32( x"8000_0004", x"5555_5555", bus_c); -- write 32 bits address of 32 bit data
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wr_32( x"8000_0004", x"5555_5555", bus_c); -- write 32 bits address of 32 bit data
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rd_32( x"8000_0004", slv_32, bus_c); -- read 32 bits address of 32 bit data
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rd_32( x"8000_0004", slv_32, bus_c); -- read 32 bits address of 32 bit data
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report to_hex( slv_32);
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report to_hex( slv_32);
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clock_wait( 2, bus_c );
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rmw_32( x"8000_0004", slv_32, x"ABCD_EF01", bus_c );
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report to_hex( slv_32);
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clock_wait( 2, bus_c );
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rmw_32( x"8000_0004", slv_32, x"01CD_EFAB", bus_c );
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report to_hex( slv_32);
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clock_wait( 1, bus_c );
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clock_wait( 1, bus_c );
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wb_rst( 2, reset_int, bus_c ); -- reset system for 2 clocks
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wb_rst( 2, reset_int, bus_c ); -- reset system for 2 clocks
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