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architecture Behavioral of wb_master is
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architecture Behavioral of wb_master is
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-- --------------------------------------------------------------------
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-- --------------------------------------------------------------------
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signal reset_int : std_logic;
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signal reset_int : std_logic;
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-- --------------------------------------------------------------------
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-- --------------------------------------------------------------------
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begin
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begin
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-- --------------------------------------------------------------------
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-- --------------------------------------------------------------------
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-- concurrent assignemente to map record to the wishbone bus
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-- concurrent assignemente to map record to the wishbone bus
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-- if we used a signal, then we get the value after the clock edge,
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-- if we used a signal, then we get the value after the clock edge,
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-- which is not what we want, we need the value at the clock edge.
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-- which is not what we want, we need the value at the clock edge.
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--
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--
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variable slv_32 : std_logic_vector( 31 downto 0);
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variable slv_32 : std_logic_vector( 31 downto 0);
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variable bka_test_array : block_type :=
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( others => x"0000_0000");
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variable bkd_test_array : block_type :=
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( others => x"0000_0000");
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begin
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begin
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-- Wait 100 ns for global reset to finish
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-- Wait 100 ns for global reset to finish
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wait for 100 ns;
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wait for 100 ns;
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Line 160... |
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wb_init( bus_c); -- initalise wishbone bus
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wb_init( bus_c); -- initalise wishbone bus
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wb_rst( 2, reset_int, bus_c ); -- reset system for 2 clocks
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wb_rst( 2, reset_int, bus_c ); -- reset system for 2 clocks
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-- set up some address / data pairs
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bka_test_array(0) := X"0000_0002";
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bkd_test_array(0) := X"5555_0002";
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wr_32( x"8000_0004", x"5555_5555", bus_c); -- write 32 bits address of 32 bit data
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bka_test_array(1) := X"0000_0004";
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bkd_test_array(1) := X"55AA_0004";
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rd_32( x"8000_0004", slv_32, bus_c); -- read 32 bits address of 32 bit data
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bka_test_array(2) := X"0000_0006";
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report to_hex( slv_32);
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bkd_test_array(2) := X"AAAA_0006";
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clock_wait( 2, bus_c );
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rmw_32( x"8000_0004", slv_32, x"ABCD_EF01", bus_c );
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bkw_32( bka_test_array, bkd_test_array, 3, bus_c);
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report to_hex( slv_32);
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clock_wait( 2, bus_c );
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clock_wait( 1, bus_c );
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bkr_32( bka_test_array, bkd_test_array, 3, bus_c);
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rmw_32( x"8000_0004", slv_32, x"01CD_EFAB", bus_c );
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report to_hex(bkd_test_array(0));
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report to_hex( slv_32);
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report to_hex(bkd_test_array(1));
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report to_hex(bkd_test_array(2));
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--
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--wr_32( x"8000_0004", x"5555_5555", bus_c); -- write 32 bits address of 32 bit data
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--
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--rd_32( x"8000_0004", slv_32, bus_c); -- read 32 bits address of 32 bit data
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--report to_hex( slv_32);
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--
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--clock_wait( 2, bus_c );
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--
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--rmw_32( x"8000_0004", slv_32, x"ABCD_EF01", bus_c );
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--report to_hex( slv_32);
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--
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--clock_wait( 2, bus_c );
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--
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--rmw_32( x"8000_0004", slv_32, x"01CD_EFAB", bus_c );
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--report to_hex( slv_32);
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--
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clock_wait( 1, bus_c );
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clock_wait( 1, bus_c );
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wb_rst( 2, reset_int, bus_c ); -- reset system for 2 clocks
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wb_rst( 2, reset_int, bus_c ); -- reset system for 2 clocks
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