URL https://opencores.org/ocsvn/wishbone_bfm/wishbone_bfm/trunk

Subversion Repositories wishbone_bfm

[/] [wishbone_bfm/] [trunk/] [rtl/] [wb_master.vhd] - Diff between revs 2 and 6

Rev 2	Rev 6
Line 145...	Line 145...
`wb_init( bus_c); -- initalise wishbone bus`	`wb_init( bus_c); -- initalise wishbone bus`
`wb_rst( 2, reset_int, bus_c ); -- reset system for 2 clocks`	`wb_rst( 2, reset_int, bus_c ); -- reset system for 2 clocks`

`wr_32( x"8000_0001", x"5555_5555", bus_c); -- write 32 bits address of 32 bit data`	`wr_32( x"8000_0001", x"5555_5555", bus_c); -- write 32 bits address of 32 bit data`

`clock_wait( 1, bus_c );`	`rd_32( x"8000_0004", slv_32, bus_c); -- read 32 bits address of 32 bit data`

	`wr_32( x"8000_0004", x"AA55_55AA", bus_c); -- write 32 bits address of 32 bit data`

`rd_32( x"8000_0004", slv_32, bus_c); -- read 32 bits address of 32 bit data`	`rd_32( x"8000_0004", slv_32, bus_c); -- read 32 bits address of 32 bit data`


`clock_wait( 5, bus_c );`	`clock_wait( 1, bus_c );`
`wb_rst( 2, reset_int, bus_c ); -- reset system for 2 clocks`	`wb_rst( 2, reset_int, bus_c ); -- reset system for 2 clocks`