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--Propery of Tecphos Inc. See License.txt for license details
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--Propery of Tecphos Inc. See License.txt for license details
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--Latest version of all project files available at http://opencores.org/project,wrimm
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--Latest version of all project files available at
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--http://opencores.org/project,wrimm
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--See WrimmManual.pdf for the Wishbone Datasheet and implementation details.
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--See WrimmManual.pdf for the Wishbone Datasheet and implementation details.
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--See wrimm subversion project for version history
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--See wrimm subversion project for version history
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------------------------------------------------------------
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--**********************************************************
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--**********************************************************
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--!!!!!!!!!!!!!!!!!! EDIT THIS FILE !!!!!!!!!!!!!!!!!
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--Save a copy of this file in a project specific directory.
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--Each project may have a different WrimmPackage.vhd file.
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--Hopefully wrimm.vhd will not require modification for each
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--project.
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-->>>>>>>>>>>>>>>>>>>>>>>Start of Customization Example>>>>>>>>>>>>>>>>>>>>>>>>>
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-- Edit or at least verify the data in all the sections of this file
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-- surrounded by the indicator lines shown above and below this text.
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--<<<<<<<<<<<<<<<<<<<<<<<End of Customization Ecample<<<<<<<<<<<<<<<<<<<<<<<<<<<
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-- Hopefully the code ouside those marked sections
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-- will not require modification.
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--**********************************************************
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--**********************************************************
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------------------------------------------------------------
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library ieee;
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library ieee;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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package WrimmPackage is
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package WrimmPackage is
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-->>>>>>>>>>>>>>>>>>>>>>>Start of Wishbone Bus Parameters >>>>>>>>>>>>>>>>>>>>>>
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constant WbAddrBits : Integer := 4;
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constant WbAddrBits : Integer := 4;
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constant WbDataBits : Integer := 8;
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constant WbDataBits : Integer := 8;
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--<<<<<<<<<<<<<<<<<<<<<<<End of Wishbone Bus Parameters <<<<<<<<<<<<<<<<<<<<<<<<
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subtype WbAddrType is std_logic_vector(0 to WbAddrBits-1);
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subtype WbAddrType is std_logic_vector(0 to WbAddrBits-1);
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subtype WbDataType is std_logic_vector(0 to WbDataBits-1);
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subtype WbDataType is std_logic_vector(0 to WbDataBits-1);
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type WbMasterOutType is record
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type WbMasterOutType is record
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Strobe : std_logic; --Required
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Strobe : std_logic; --Required
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WrEn : std_logic;
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WrEn : std_logic; --Required
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Addr : WbAddrType;
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Addr : WbAddrType; --Required
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Data : WbDataType;
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Data : WbDataType;
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--DataTag : std_logic_vector(0 to 1); --Write,Set,Clear,Toggle
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--DataTag : std_logic_vector(0 to 1); --Write,Set,Clear,Toggle
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Cyc : std_logic; --Required
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Cyc : std_logic; --Required
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--CycType : std_logic_vector(0 to 2); --For Burst Cycles
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--CycType : std_logic_vector(0 to 2); --For Burst Cycles
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end record WbMasterOutType;
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end record WbMasterOutType;
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Err : std_logic;
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Err : std_logic;
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Rty : std_logic;
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Rty : std_logic;
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Data : WbDataType;
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Data : WbDataType;
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end record WbSlaveOutType;
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end record WbSlaveOutType;
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--=============================================================================
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--==========================================================
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-------------------------------------------------------------------------------
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------------------------------------------------------------
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-- Master Interfaces
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-- Master Interfaces: provides interfaces for 1-n Masters
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-------------------------------------------------------------------------------
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------------------------------------------------------------
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type WbMasterType is (
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type WbMasterType is (
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-->>>>>>>>>>>>>>>>>>>>>>>Start of Wishbone Master List >>>>>>>>>>>>>>>>>>>>>>>>>
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Q,
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Q,
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P);
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P);
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--<<<<<<<<<<<<<<<<<<<<<<<End of Wishbone Master List <<<<<<<<<<<<<<<<<<<<<<<<<<<
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type WbMasterOutArray is array (WbMasterType) of WbMasterOutType;
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type WbMasterOutArray is array (WbMasterType) of WbMasterOutType;
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type WbSlaveOutArray is array (WbMasterType) of WbSlaveOutType;
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type WbSlaveOutArray is array (WbMasterType) of WbSlaveOutType;
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type WbMasterGrantType is Array (WbMasterType'left to WbMasterType'right) of std_logic;
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type WbMasterGrantType is Array (WbMasterType'left to WbMasterType'right) of std_logic;
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--=============================================================================
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--==========================================================
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-------------------------------------------------------------------------------
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------------------------------------------------------------
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-- Status Registers (Report internal results)
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-- Status Registers: Report results from other modules
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-------------------------------------------------------------------------------
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------------------------------------------------------------
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type StatusFieldParams is record
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type StatusFieldParams is record
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BitWidth : integer;
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BitWidth : integer;
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MSBLoc : integer;
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MSBLoc : integer;
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Address : WbAddrType;
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Address : WbAddrType;
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end record StatusFieldParams;
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end record StatusFieldParams;
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type StatusFieldType is (
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type StatusFieldType is (
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-->>>>>>>>>>>>>>>>>>>>>>>Start of Status Field List >>>>>>>>>>>>>>>>>>>>>>>>>>>>
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StatusA,
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StatusA,
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StatusB,
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StatusB,
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StatusC);
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StatusC);
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--<<<<<<<<<<<<<<<<<<<<<<<End of Status Field List <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
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type StatusArrayType is Array (StatusFieldType'left to StatusFieldType'right) of WbDataType;
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type StatusArrayType is Array (StatusFieldType'left to StatusFieldType'right) of WbDataType;
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type StatusArrayBitType is Array (StatusFieldType'left to StatusFieldType'right) of std_logic;
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type StatusArrayBitType is Array (StatusFieldType'left to StatusFieldType'right) of std_logic;
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type StatusFieldDefType is Array (StatusFieldType'left to StatusFieldType'right) of StatusFieldParams;
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type StatusFieldDefType is Array (StatusFieldType'left to StatusFieldType'right) of StatusFieldParams;
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constant StatusParams : StatusFieldDefType :=(
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constant StatusParams : StatusFieldDefType :=(
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-->>>>>>>>>>>>>>>>>>>>>>>Start of Status Field Parameters >>>>>>>>>>>>>>>>>>>>>>
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StatusA => (BitWidth => 8, MSBLoc => 0, Address => x"0"),
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StatusA => (BitWidth => 8, MSBLoc => 0, Address => x"0"),
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StatusB => (BitWidth => 8, MSBLoc => 0, Address => x"1"),
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StatusB => (BitWidth => 8, MSBLoc => 0, Address => x"1"),
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StatusC => (BitWidth => 8, MSBLoc => 0, Address => x"2"));
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StatusC => (BitWidth => 8, MSBLoc => 0, Address => x"2"));
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--=============================================================================
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--<<<<<<<<<<<<<<<<<<<<<<<End of Status Field Parameters <<<<<<<<<<<<<<<<<<<<<<<<
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-------------------------------------------------------------------------------
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--==========================================================
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-- Setting Registers
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------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- Setting Registers: Provide config bits to other modules
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------------------------------------------------------------
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type SettingFieldParams is record
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type SettingFieldParams is record
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BitWidth : integer;
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BitWidth : integer;
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MSBLoc : integer;
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MSBLoc : integer;
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Address : WbAddrType;
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Address : WbAddrType;
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Default : WbDataType;
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Default : WbDataType;
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end record SettingFieldParams;
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end record SettingFieldParams;
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type SettingFieldType is (
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type SettingFieldType is (
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-->>>>>>>>>>>>>>>>>>>>>>>Start of Setting Field List >>>>>>>>>>>>>>>>>>>>>>>>>>>
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SettingX,
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SettingX,
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SettingY,
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SettingY,
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SettingZ);
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SettingZ);
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--<<<<<<<<<<<<<<<<<<<<<<<End of Setting Field List <<<<<<<<<<<<<<<<<<<<<<<<<<<<<
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type SettingArrayType is Array (SettingFieldType'Left to SettingFieldType'Right) of WbDataType;
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type SettingArrayType is Array (SettingFieldType'Left to SettingFieldType'Right) of WbDataType;
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type SettingArrayBitType is Array (SettingFieldType'Left to SettingFieldType'Right) of std_logic;
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type SettingArrayBitType is Array (SettingFieldType'Left to SettingFieldType'Right) of std_logic;
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type SettingFieldDefType is Array (SettingFieldType'Left to SettingFieldType'Right) of SettingFieldParams;
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type SettingFieldDefType is Array (SettingFieldType'Left to SettingFieldType'Right) of SettingFieldParams;
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constant SettingParams : SettingFieldDefType :=(
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constant SettingParams : SettingFieldDefType :=(
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-->>>>>>>>>>>>>>>>>>>>>>>Start of Setting Field Parameters >>>>>>>>>>>>>>>>>>>>>
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SettingX => (BitWidth => 8, MSBLoc => 0, Address => x"6", Default => x"05"),
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SettingX => (BitWidth => 8, MSBLoc => 0, Address => x"6", Default => x"05"),
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SettingY => (BitWidth => 8, MSBLoc => 0, Address => x"7", Default => x"3C"),
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SettingY => (BitWidth => 8, MSBLoc => 0, Address => x"7", Default => x"3C"),
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SettingZ => (BitWidth => 8, MSBLoc => 0, Address => x"8", Default => x"AA"));
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SettingZ => (BitWidth => 8, MSBLoc => 0, Address => x"8", Default => x"AA"));
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--=============================================================================
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--<<<<<<<<<<<<<<<<<<<<<<<End of Setting Field Parameters<<<<<<<<<<<<<<<<<<<<<<<<
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-------------------------------------------------------------------------------
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--==========================================================
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-- Trigger Registers (Report internal results)
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------------------------------------------------------------
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-------------------------------------------------------------------------------
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-- Trigger Registers, Launch other processes, cleared by those processes
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------------------------------------------------------------
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type TriggerFieldParams is record
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type TriggerFieldParams is record
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BitLoc : integer;
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BitLoc : integer;
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Address : WbAddrType;
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Address : WbAddrType;
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end record TriggerFieldParams;
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end record TriggerFieldParams;
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type TriggerFieldType is (
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type TriggerFieldType is (
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-->>>>>>>>>>>>>>>>>>>>>>>Start of Trigger List >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>>
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TriggerR,
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TriggerR,
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TriggerS,
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TriggerS,
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TriggerT);
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TriggerT);
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--<<<<<<<<<<<<<<<<<<<<<<<End of Trigger List <<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<<
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type TriggerArrayType is Array (TriggerFieldType'Left to TriggerFieldType'Right) of std_logic;
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type TriggerArrayType is Array (TriggerFieldType'Left to TriggerFieldType'Right) of std_logic;
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type TriggerFieldDefType is Array (TriggerFieldType'Left to TriggerFieldType'Right) of TriggerFieldParams;
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type TriggerFieldDefType is Array (TriggerFieldType'Left to TriggerFieldType'Right) of TriggerFieldParams;
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constant TriggerParams : TriggerFieldDefType :=(
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constant TriggerParams : TriggerFieldDefType :=(
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-->>>>>>>>>>>>>>>>>>>>>>>Start of Trigger Parameters >>>>>>>>>>>>>>>>>>>>>>>>>>>
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TriggerR => (BitLoc => 7, Address => x"A"),
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TriggerR => (BitLoc => 7, Address => x"A"),
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TriggerS => (BitLoc => 7, Address => x"B"),
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TriggerS => (BitLoc => 7, Address => x"B"),
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TriggerT => (BitLoc => 7, Address => x"C"));
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TriggerT => (BitLoc => 7, Address => x"C"));
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--<<<<<<<<<<<<<<<<<<<<<<<End of Trigger Parameters <<<<<<<<<<<<<<<<<<<<<<<<<<<<<
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end package WrimmPackage;
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end package WrimmPackage;
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--package body WishBonePackage is
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--package body WishBonePackage is
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--
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--
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--
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-- No package functions (yet)
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--
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--
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--end package body WishBonePackage;
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--end package body WishBonePackage;
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No newline at end of file
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No newline at end of file
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