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--See wrimm subversion project for version history
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--See wrimm subversion project for version history
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library ieee;
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library ieee;
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use ieee.NUMERIC_STD.all;
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use ieee.NUMERIC_STD.all;
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use ieee.std_logic_1164.all;
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use ieee.std_logic_1164.all;
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use std.textio.all;
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use work.WrimmPackage.all;
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use work.WrimmPackage.all;
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entity wrimm_top_tb is
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entity WrimmTestBench is
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end wrimm_top_tb;
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end WrimmTestBench;
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architecture TB_ARCHITECTURE of wrimm_top_tb is
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architecture TbArch of WrimmTestBench is
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component wrimm_top
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component Wrimm is
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port(
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port(
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WishboneClock : in std_logic;
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WbClk : in std_logic;
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WishboneReset : out std_logic;
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WbRst : out std_logic;
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MasterPStrobe : in std_logic;
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WbMasterIn : in WbMasterOutArray; --Signals from Masters
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MasterPWrEn : in std_logic;
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WbMasterOut : out WbSlaveOutArray; --Signals to Masters
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MasterPCyc : in std_logic;
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--WbSlaveIn : out WbMasterOutArray;
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MasterPAddr : in WbAddrType;
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--WbSlaveOut : in WbSlaveOutArray;
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MasterPDataToSlave : in WbDataType;
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StatusRegs : in StatusArrayType;
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MasterPAck : out std_logic;
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SettingRegs : out SettingArrayType;
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MasterPErr : out std_logic;
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SettingRsts : in SettingArrayBitType;
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MasterPRty : out std_logic;
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Triggers : out TriggerArrayType;
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MasterPDataFrSlave : out WbDataType;
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TriggerClr : in TriggerArrayType;
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MasterQStrobe : in std_logic;
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rstZ : in std_logic); --Asynchronous reset
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MasterQWrEn : in std_logic;
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end component Wrimm;
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MasterQCyc : in std_logic;
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MasterQAddr : in WbAddrType;
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signal wbMastersOut : WbSlaveOutArray;
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MasterQDataToSlave : in WbDataType;
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signal wbMastersIn : WbMasterOutArray;
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MasterQAck : out std_logic;
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signal statusRegs : StatusArrayType;
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MasterQErr : out std_logic;
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signal settingRegs : SettingArrayType;
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MasterQRty : out std_logic;
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signal settingRsts : SettingArrayBitType;
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MasterQDataFrSlave : out WbDataType;
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signal triggers : TriggerArrayType;
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StatusRegA : in std_logic_vector(0 to 7);
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signal triggerClrs : TriggerArrayType;
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StatusRegB : in std_logic_vector(0 to 7);
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StatusRegC : in std_logic_vector(0 to 7);
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SettingRegX : out std_logic_vector(0 to 7);
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SettingRstX : in std_logic;
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SettingRegY : out std_logic_vector(0 to 7);
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SettingRstY : in std_logic;
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SettingRegZ : out std_logic_vector(0 to 7);
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SettingRstZ : in std_logic;
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TriggerRegR : out std_logic;
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TriggerClrR : in std_logic;
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TriggerRegS : out std_logic;
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TriggerClrS : in std_logic;
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TriggerRegT : out std_logic;
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TriggerClrT : in std_logic;
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rstZ : in std_logic);
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end component;
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signal WishboneClock : std_logic;
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signal MasterPStrobe : std_logic;
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signal MasterPWrEn : std_logic;
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signal MasterPCyc : std_logic;
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signal MasterPAddr : WbAddrType;
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signal MasterPDataToSlave : WbDataType;
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signal MasterQStrobe : std_logic;
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signal MasterQWrEn : std_logic;
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signal MasterQCyc : std_logic;
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signal MasterQAddr : WbAddrType;
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signal MasterQDataToSlave : WbDataType;
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signal StatusRegA : std_logic_vector(0 to 7);
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signal StatusRegB : std_logic_vector(0 to 7);
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signal StatusRegC : std_logic_vector(0 to 7);
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signal SettingRstX : std_logic;
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signal SettingRstY : std_logic;
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signal SettingRstZ : std_logic;
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signal TriggerClrR : std_logic;
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signal TriggerClrS : std_logic;
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signal TriggerClrT : std_logic;
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signal rstZ : std_logic;
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signal rstZ : std_logic;
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signal WishboneReset : std_logic;
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signal WishboneClock : std_logic;
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signal MasterPAck : std_logic;
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signal WishBoneReset : std_logic;
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signal MasterPErr : std_logic;
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signal MasterPRty : std_logic;
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signal MasterPDataFrSlave : WbDataType;
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signal MasterQAck : std_logic;
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signal MasterQErr : std_logic;
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signal MasterQRty : std_logic;
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signal MasterQDataFrSlave : WbDataType;
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signal SettingRegX : std_logic_vector(0 to 7);
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signal SettingRegY : std_logic_vector(0 to 7);
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signal SettingRegZ : std_logic_vector(0 to 7);
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signal TriggerRegR : std_logic;
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signal TriggerRegS : std_logic;
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signal TriggerRegT : std_logic;
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constant clkPeriod : time := 0.01 us; --100 MHz
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constant clkPeriod : time := 0.01 us; --100 MHz
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begin
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begin
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UUT : wrimm_top
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port map (
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WishboneClock => WishboneClock,
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WishboneReset => WishboneReset,
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MasterPStrobe => MasterPStrobe,
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MasterPWrEn => MasterPWrEn,
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MasterPCyc => MasterPCyc,
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MasterPAddr => MasterPAddr,
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MasterPDataToSlave => MasterPDataToSlave,
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MasterPAck => MasterPAck,
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MasterPErr => MasterPErr,
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MasterPRty => MasterPRty,
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MasterPDataFrSlave => MasterPDataFrSlave,
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MasterQStrobe => MasterQStrobe,
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MasterQWrEn => MasterQWrEn,
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MasterQCyc => MasterQCyc,
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MasterQAddr => MasterQAddr,
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MasterQDataToSlave => MasterQDataToSlave,
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MasterQAck => MasterQAck,
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MasterQErr => MasterQErr,
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MasterQRty => MasterQRty,
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MasterQDataFrSlave => MasterQDataFrSlave,
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StatusRegA => StatusRegA,
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StatusRegB => StatusRegB,
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StatusRegC => StatusRegC,
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SettingRegX => SettingRegX,
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SettingRstX => SettingRstX,
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SettingRegY => SettingRegY,
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SettingRstY => SettingRstY,
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SettingRegZ => SettingRegZ,
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SettingRstZ => SettingRstZ,
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TriggerRegR => TriggerRegR,
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TriggerClrR => TriggerClrR,
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TriggerRegS => TriggerRegS,
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TriggerClrS => TriggerClrS,
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TriggerRegT => TriggerRegT,
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TriggerClrT => TriggerClrT,
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rstZ => rstZ);
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procClk: process
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procClk: process
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begin
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begin
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if WishBoneClock='1' then
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if WishBoneClock='1' then
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WishBoneClock <= '0';
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WishBoneClock <= '0';
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else
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else
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| Line 148... |
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wait for 10 ns;
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wait for 10 ns;
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rstZ <= '1';
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rstZ <= '1';
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wait;
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wait;
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end process procRstZ;
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end process procRstZ;
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procWbMasterP: process
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instWrimm: Wrimm
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port map(
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WbClk => WishboneClock,
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WbRst => WishboneReset,
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WbMasterIn => wbMastersIn,
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WbMasterOut => wbMastersOut,
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--WbSlaveIn => ,
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--WbSlaveOut => ,
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StatusRegs => statusRegs,
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SettingRegs => settingRegs,
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SettingRsts => settingRsts,
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Triggers => triggers,
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TriggerClr => triggerClrs,
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rstZ => rstZ);
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procStatusStim: process(WishboneClock) is
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variable statusCount : unsigned (0 to WbDataBits-1) := (Others=>'0');
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begin
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begin
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MasterPStrobe <= '0';
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if rising_edge(WishboneClock) then
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MasterPWrEn <= '0';
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loopStatusAssign: for i in StatusFieldType loop
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MasterPCyc <= '0';
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statusRegs(i) <= std_logic_vector(statusCount);
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MasterPAddr <= x"0";
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statusCount := statusCount + 1; --actual values don't matter, just generating unique values.
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MasterPDataToSlave <= x"00";
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end loop loopStatusAssign;
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wait for clkPeriod / 10;
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end if; --Clk
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wait for clkPeriod * 5;
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end process procStatusStim;
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MasterPStrobe <= '1';
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MasterPWrEn <= '1';
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procStatusVerify: process(WishboneClock) is
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MasterPCyc <= '1';
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variable L : line;
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MasterPAddr <= x"6";
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begin
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MasterPDataToSlave <= x"55";
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if rising_edge(WishBoneClock) then
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wait for clkPeriod * 2;
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loopMasters: for i in WbMasterType loop
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MasterPStrobe <= '0';
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if wbMastersOut(i).Ack='1' and wbMastersIn(i).WrEn='0' then --valid Ack to Read request
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MasterPWrEn <= '0';
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loopStatusRegs: for j in StatusFieldType loop
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MasterPCyc <= '0';
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if StatusParams(j).Address=wbMastersIn(i).Addr then --correct address
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MasterPAddr <= x"0";
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report "Evaluating Status Read" severity NOTE;
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MasterPDataToSlave <= x"00";
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assert (statusRegs(j)=wbMastersOut(i).data) report "Invalid Status Register Read" severity Warning;
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wait for clkPeriod * 10;
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end if;
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MasterPStrobe <= '1';
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end loop loopStatusRegs;
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MasterPWrEn <= '1';
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end if; -- valid Ack
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MasterPCyc <= '1';
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end loop loopMasters;
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MasterPAddr <= x"6";
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end if; --Clk
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MasterPDataToSlave <= x"99";
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end process procStatusVerify;
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wait for clkPeriod * 2;
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MasterPStrobe <= '0';
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procSettingResets: process(WishboneClock) is
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MasterPWrEn <= '0';
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variable resetVector : unsigned(0 to settingRsts'length-1) := (Others=>'0');
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MasterPCyc <= '0';
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variable resetCount : integer := 0;
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MasterPAddr <= x"0";
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variable resetIndex : integer := 0;
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MasterPDataToSlave <= x"00";
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wait;
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end process procWbMasterP;
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procWbMasterQ: process
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begin
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begin
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MasterQStrobe <= '0';
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if rising_edge(WishboneClock) then
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MasterQWrEn <= '0';
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if resetCount=20 then
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MasterQCyc <= '0';
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resetCount := 0;
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MasterQAddr <= x"0";
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resetVector := resetVector+1;
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MasterQDataToSlave <= x"00";
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resetIndex := 0;
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wait for clkPeriod / 10;
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loopSetRsts: for i in SettingFieldType loop
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wait for clkPeriod * 8;
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settingRsts(i) <= resetVector(resetIndex);
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MasterQStrobe <= '1';
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resetIndex := resetIndex + 1;
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MasterQWrEn <= '1';
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end loop loopSetRsts;
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MasterQCyc <= '1';
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else
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MasterQAddr <= x"6";
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resetCount := resetCount + 1;
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MasterQDataToSlave <= x"77";
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settingRsts <= (Others=>'0');
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wait for clkPeriod * 2;
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end if;
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MasterQStrobe <= '0';
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end if; --Clk
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MasterQWrEn <= '0';
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end process procSettingResets;
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MasterQCyc <= '0';
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MasterQAddr <= x"0";
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procSettingMonitor: process(WishboneClock,rstZ) is
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MasterQDataToSlave <= x"00";
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variable settingTBRegs : SettingArrayType;
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wait for clkPeriod * 2;
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begin
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assert false report "Test Complete" severity warning;
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if (rstZ='0') then
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end process procWbMasterQ;
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loopSettingRstZ: for i in SettingFieldType loop
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settingTBRegs(i) := SettingParams(i).Default;
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end TB_ARCHITECTURE;
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end loop loopSettingRstZ;
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elsif rising_edge(WishboneClock) then
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configuration TESTBENCH_FOR_wrimm_top of wrimm_top_tb is
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loopSettingRegsCheck : for k in SettingFieldType loop
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for TB_ARCHITECTURE
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assert (settingTBRegs(k)=settingRegs(k)) report "Setting Reg Mismatch" severity Warning;
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for UUT : wrimm_top
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end loop loopSettingRegsCheck;
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use entity work.wrimm_top(structure);
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loopMasters: for i in WbMasterType loop --valid Ack
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end for;
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if wbMastersOut(i).Ack='1' then
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end for;
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if wbMastersIn(i).WrEn='1' then -- Write request
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end TESTBENCH_FOR_wrimm_top;
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loopSettingWriteRegs: for j in SettingFieldType loop
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if SettingParams(j).Address=wbMastersIn(i).Addr then --valid setting address
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report "Writing Setting Reg";
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settingTBRegs(j) := wbMastersIn(i).data;
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end if; --Address match
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end loop loopSettingWriteRegs;
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else -- Read request
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loopSettingReadRegs: for j in SettingFieldType loop
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if SettingParams(j).Address=wbMastersIn(i).Addr then --valid setting address
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report "Reading Setting Reg";
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assert (wbMastersOut(i).data=settingTBRegs(j)) report "Setting Read Mismatch" severity Warning;
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end if; --Address match
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end loop loopSettingReadRegs;
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end if; --WrEn
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end if; --Ack to write
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end loop loopMasters;
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loopSettingResets: for i in SettingFieldType loop
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if settingRsts(i)='1' then
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settingTBRegs(i) := SettingParams(i).Default;
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end if;
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end loop loopSettingResets;
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end if; --Clk
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end process procSettingMonitor;
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procMasterStim: process(WishboneClock,rstZ) is
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variable rCount : unsigned(0 to WbAddrBits) := (Others=>'0');
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variable rData : unsigned(0 to WbDataBits-1) := (Others=>'0');
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variable burstCount : integer := 5;
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variable idleCount : integer := 4;
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begin
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if rising_edge(WishboneClock) then
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rData := rData + 1;
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if WbMastersOut(Q).Ack='1' or WbMastersOut(Q).Rty='1' or WbMastersOut(Q).Err='1' then
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rCount := rCount + 1;
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burstCount := burstcount - 1;
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if burstCount=0 then
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idleCount := 3;
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end if;
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elsif idleCount=0 then
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if burstCount=0 then
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burstCount := 4;
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end if;
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else
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idleCount := idleCount - 1;
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end if;
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wbMastersIn(Q).Data <= std_logic_vector(rData);
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wbMastersIn(Q).Addr <= std_logic_vector(rCount(1 to WbAddrBits));
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wbMastersIn(Q).WrEn <= rCount(0); --read then write
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if burstCount=0 then
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wbMastersIn(Q).Strobe <= '0';
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wbMastersIn(Q).Cyc <= '0';
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else
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wbMastersIn(Q).Strobe <= '1';
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wbMastersIn(Q).Cyc <= '1';
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end if;
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end if; --Clk
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end process procMasterStim;
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end TbArch;
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No newline at end of file
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No newline at end of file
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