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Line 28... |
#include <stdio.h>
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#include <stdio.h>
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#include <xspi.h>
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#include <xspi.h>
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#include "spansion_flash.h"
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#include "spansion_flash.h"
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#include "uprintf.h"
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#include "uprintf.h"
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#define SPANSION_CFG_REG_QUAD (1<<1)
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#define SPANSION_CFG_REG_OTP_MASK (0x3c)
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#define SPANSION_BANK_REG_EXT_ADDR (1<<7)
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#define SPANSION_CFG_REG_BP_SHIFT 2
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#define SPANSION_CFG_REG_BP_MASK (0x7 << SPANSION_CFG_REG_BP_SHIFT)
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#define SPANSION_STAT_REG_WIP (1<<0)
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#define SPANSION_CFG_REG_LC_MASK (0xc0)
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#define SPANSION_CFG_REG_LC_DEFAULT 0
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static int spansion_flash_cmd_wen(struct spansion_flash *sf);
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static int spansion_flash_get_cr1(struct spansion_flash *sf, u8 *cr1);
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static int spansion_flash_get_sr1(struct spansion_flash *sf, u8 *sr1);
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int spansion_flash_init (struct spansion_flash *sf, XSpi *spi, int slave_num)
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int spansion_flash_init (struct spansion_flash *sf, XSpi *spi, int slave_num)
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{
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{
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u8 rCfg;
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sf->spi = spi;
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sf->spi = spi;
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sf->slave_select = (1<<slave_num);
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sf->slave_select = (1<<slave_num);
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int res;
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int ret;
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res = XSpi_SetOptions(sf->spi, (XSP_MASTER_OPTION | \
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ret = XSpi_SetOptions(sf->spi, (XSP_MASTER_OPTION | \
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XSP_MANUAL_SSELECT_OPTION | \
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XSP_MANUAL_SSELECT_OPTION | \
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XSP_CLK_PHASE_1_OPTION | \
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XSP_CLK_PHASE_1_OPTION | \
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XSP_CLK_ACTIVE_LOW_OPTION));
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XSP_CLK_ACTIVE_LOW_OPTION));
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if(res)
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if(ret)
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return res;
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return ret;
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res = XSpi_SetSlaveSelect(sf->spi, sf->slave_select);
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ret = XSpi_SetSlaveSelect(sf->spi, sf->slave_select);
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if(res)
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if(ret)
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return res;
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return ret;
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res = XSpi_Start(sf->spi);
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ret = XSpi_Start(sf->spi);
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return res;
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if (ret)
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return ret;
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/* Put spi to polled mode */
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XSpi_IntrGlobalDisable(sf->spi);
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/* Check latency is as expected */
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ret = spansion_flash_get_cr1(sf, &rCfg);
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if(ret)
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return ret;
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if ((rCfg & SPANSION_CFG_REG_LC_MASK) != SPANSION_CFG_REG_LC_DEFAULT) {
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uprintf("Flash is configured with non-default latency code. Cannot read flash\r\n");
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return -1;
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}
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return 0;
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}
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}
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static int spansion_flash_transfer(struct spansion_flash *sf, uint8_t *wr_buf, uint8_t *rd_buf, int len)
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static int spansion_flash_transfer(struct spansion_flash *sf, uint8_t *wr_buf, uint8_t *rd_buf, int len)
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{
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{
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int res;
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int res;
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Line 90... |
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return XST_SUCCESS;
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return XST_SUCCESS;
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}
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}
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/* Get status and control register and set QSPI*/
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/*
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* Get status and control register value
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* and set QSPI mode. It needs to be done
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* after each configuration flash programming
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* using Xilinx tools as they erase this flag.
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*
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* !!!BEWARE: This is potentially dangerous
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* operation as if power is lost during write to
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* status and configuration register, both can be
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* set to all ones. It may set OTP bits that may render
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* flash unusable. As quad mode flag is non-volatile
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* it is necessary to do this once only during board
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*
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*/
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int spansion_flash_quad_mode(struct spansion_flash *sf)
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int spansion_flash_quad_mode(struct spansion_flash *sf)
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{
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{
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#define SPANSION_CFG_REG_QUAD (1<<1)
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int ret;
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int ret;
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u8 rCfgBuf[2];
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int tmo_cnt;
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u8 rStBuf[2];
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u8 rCfg;
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u8 rSt;
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u8 wCfgBuf[3];
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u8 wCfgBuf[3];
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u8 wEnBuf[1];
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rCfgBuf[0] = 0x35;
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ret = spansion_flash_get_cr1(sf, &rCfg);
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ret = spansion_flash_transfer(sf, rCfgBuf, rCfgBuf, 2);
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if(ret)
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if(ret)
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return ret;
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return ret;
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rStBuf[0] = 0x05;
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if (rCfg & SPANSION_CFG_REG_QUAD) {
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ret = spansion_flash_transfer(sf, rStBuf, rStBuf, 2);
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return 0;
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}
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ret = spansion_flash_get_sr1(sf, &rSt);
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if(ret)
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if(ret)
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return ret;
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return ret;
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wEnBuf[0] = 0x6;
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ret = spansion_flash_cmd_wen(sf);
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ret = spansion_flash_transfer(sf, wEnBuf, wEnBuf, 1);
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if(ret)
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if(ret)
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return ret;
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return ret;
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uprintf("WARNING: Setting flash quad mode in flash configuration\r\n"
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"registers. If power is lost at that moment flash can be\r\n"
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"corrupted permanently.\r\n");
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wCfgBuf[0] = 0x01;
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wCfgBuf[0] = 0x01;
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wCfgBuf[1] = rStBuf[1];
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wCfgBuf[1] = rSt;
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wCfgBuf[2] = rCfgBuf[1] | SPANSION_CFG_REG_QUAD;
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wCfgBuf[2] = rCfg | SPANSION_CFG_REG_QUAD;
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ret = spansion_flash_transfer(sf, wCfgBuf, wCfgBuf, 3);
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ret = spansion_flash_transfer(sf, wCfgBuf, wCfgBuf, 3);
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if(ret)
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if(ret)
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return ret;
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return ret;
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/* Reread CFG reg */
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/* Wait until flash finishes write with timeout */
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rCfgBuf[0] = 0x35;
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tmo_cnt = 1000;
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ret = spansion_flash_transfer(sf, rCfgBuf, rCfgBuf, 2);
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do {
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ret = spansion_flash_get_sr1(sf, &rSt);
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if(ret)
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if(ret)
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return ret;
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return ret;
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return 0;
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if(tmo_cnt)
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}
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tmo_cnt--;
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else
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/* Set extended addressing mode in Flash and in Xilisf */
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return -1;
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/* !!! Doesn't work well for quad command 6b */
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} while (rSt & SPANSION_STAT_REG_WIP);
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int spansion_flash_extended_addressing(struct spansion_flash *sf, int onOff)
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{
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#define SPANSION_BANK_REG_EXT_ADDR (1<<7)
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int ret;
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u8 buf[2];
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XSpi *spi = sf->spi;
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/* Read bank register*/
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/* Reread CFG reg */
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buf[0] = 0x16;
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ret = spansion_flash_get_cr1(sf, &rCfg);
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ret = XSpi_Transfer(spi, buf, buf, 2);
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if(ret)
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if(ret)
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return ret;
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return ret;
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/* Write bank register with extended addressing setting */
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if (rCfg & SPANSION_CFG_REG_QUAD) {
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buf[0] = 0x17;
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uprintf("Flash quad mode set successfully.\r\n");
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if (onOff) {
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return 0;
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buf[1] |= SPANSION_BANK_REG_EXT_ADDR;
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} else {
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} else {
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buf[1] &= ~SPANSION_BANK_REG_EXT_ADDR;
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uprintf("Flash quad mode was not set, cannot read flash.\r\n");
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return -1;
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}
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}
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ret = XSpi_Transfer(spi, buf, buf, 2);
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if(ret)
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return ret;
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/* Read bank register*/
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buf[0] = 0x16;
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ret = XSpi_Transfer(spi, buf, buf, 2);
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if(ret)
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return ret;
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uprintf("Modified bank register 0x%02x\r\n", buf[1]);
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return 0;
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}
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}
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/*
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/*
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* Use Quad IO 4 byte address read command to read block of data.
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* Use Quad IO 4 byte address read command to read block of data.
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* spi - SPI core instance to be used
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* spi - SPI core instance to be used
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* flash_addr - 32 bit start address in flash
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* flash_addr - 32 bit start address in flash
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* buf - pointer to buffer where data shall be stored; must be 8 byte longer then length of data
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* buf - pointer to buffer where data shall be stored; must be 8 byte longer then length of data
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Line 197... |
*(cmdbuf++) = 0;
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*(cmdbuf++) = 0;
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return XSpi_Transfer(spi, buf, buf, len + 8);
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return XSpi_Transfer(spi, buf, buf, len + 8);
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}
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}
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No newline at end of file
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No newline at end of file
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/*
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* Read and print flash configuration and status.
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*/
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int spansion_flash_print_status(struct spansion_flash *sf)
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{
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int ret;
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u8 rCfgBuf[2];
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u8 rStBuf[2];
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u8 rRDID[4];
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rRDID[0] = 0x9f;
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ret = spansion_flash_transfer(sf, rRDID, rRDID, 4);
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if(ret)
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return ret;
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uprintf("RDID: 0x%02x 0x%02x 0x%02x\r\n", rRDID[1], rRDID[2], rRDID[3]);
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rStBuf[0] = 0x05;
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ret = spansion_flash_transfer(sf, rStBuf, rStBuf, 2);
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if(ret)
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return ret;
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uprintf("Status reg 1: 0x%02x\r\n", rStBuf[1]);
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rStBuf[0] = 0x07;
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ret = spansion_flash_transfer(sf, rStBuf, rStBuf, 2);
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if(ret)
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return ret;
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uprintf("Status reg 2: 0x%02x\r\n", rStBuf[1]);
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rCfgBuf[0] = 0x35;
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ret = spansion_flash_transfer(sf, rCfgBuf, rCfgBuf, 2);
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if(ret)
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return ret;
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uprintf("Configuration reg: 0x%02x\r\n", rCfgBuf[1]);
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return 0;
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}
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/* Send write enable command - needed for register write */
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static int spansion_flash_cmd_wen(struct spansion_flash *sf)
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{
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int ret;
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u8 wEnBuf[1];
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wEnBuf[0] = 0x6;
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ret = spansion_flash_transfer(sf, wEnBuf, wEnBuf, 1);
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return ret;
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}
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/* Send Bulk erase command*/
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static int spansion_flash_cmd_be(struct spansion_flash *sf)
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{
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int ret;
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u8 buf[1];
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buf[0] = 0x60;
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ret = spansion_flash_transfer(sf, buf, buf, 1);
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return ret;
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}
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/* Send get status register sr1*/
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static int spansion_flash_get_sr1(struct spansion_flash *sf, u8 *sr1)
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{
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int ret;
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u8 rStBuf[2];
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rStBuf[0] = 0x05;
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ret = spansion_flash_transfer(sf, rStBuf, rStBuf, 2);
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*sr1 = rStBuf[1];
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return ret;
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}
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/* Send get configuration register */
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static int spansion_flash_get_cr1(struct spansion_flash *sf, u8 *cr1)
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{
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int ret;
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u8 rCfgBuf[2];
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rCfgBuf[0] = 0x35;
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ret = spansion_flash_transfer(sf, rCfgBuf, rCfgBuf, 2);
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*cr1 = rCfgBuf[1];
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return ret;
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}
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/*
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* Erase whole device using bulk erase.
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*/
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int spansion_flash_bulk_erase(struct spansion_flash *sf)
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{
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int ret;
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u8 sr;
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int i;
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ret = spansion_flash_cmd_wen(sf);
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if(ret)
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return ret;
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ret = spansion_flash_cmd_be(sf);
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if(ret)
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return ret;
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i = 0;
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do {
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ret = spansion_flash_get_sr1(sf, &sr);
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i++;
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} while (sr & SPANSION_STAT_REG_WIP);
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return ret;
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}
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No newline at end of file
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No newline at end of file
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