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[/] [xgate/] [trunk/] [README.txt] - Diff between revs 2 and 5

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Sept 10,2009
 
Added WISHBONE master bus submodule and some related top level signals but still
 
  not much real functionality.
 
 
 
Added code to allow for memory access stalls.
 
 
 
Upgraded testbench to insert memory wait states. Added more error detection
 
  and summery.
 
 
 
Improved instruction decoder. Still needs more work to remove redundant adders
 
  to improve synthesis results.
 
 
 
 
Sept 1, 2009
Sept 1, 2009
This is a prerelease checkin and should be looked at as an incremental backup
This is a prerelease checkin and should be looked at as an incremental backup
and not representative of what may be in the final release.
and not representative of what may be in the final release.
 
 
RTL - 75% done
RTL - 75% done
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What's broken or unimplemented:
What's broken or unimplemented:
  All things related to debug mode.
  All things related to debug mode.
  WISHBONE master bus interface.
  WISHBONE master bus interface.
 
 
User Documentation - 30% done
User Documentation - 30% done
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