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// 45678901234567890123456789012345678901234567890123456789012345678901234567890
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// 45678901234567890123456789012345678901234567890123456789012345678901234567890
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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// SVN tag: None
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// SVN tag: None
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Jan 27,2010
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RTL - 85% done -- Fixed error in wbs_ack_o signal when Xgate wait states were
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enabled. If a slave bus transaction was started but not completed in the
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second cycle a wbs_ack_o output was still generated. Added a wbs_err_o output
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signal to flag this input condition but not sure if it is really needed.
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The old testbench was "helping" the Xgate module by sending an almost
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continuous wbm_ack_i signal which allowed the RISC state machine to advance
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when it shouldn't. Changes were made to the WISHBONE master bus interface
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and the RISC control logic.
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Updates to testbench -- Extensive changes to testbench. The bus arbitration
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module has been completely rewritten. It now completely controls access to the
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system bus and RAM. It internally generates a WISHBONE ack signal for the RAM.
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The test control registers have been moved out of the top level and put into
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a new WISHBONE slave module which also attaches to the system bus. The Xgate
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modules master and slave buses are fully integrated with the bus arbitration
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module and the system bus. The new testbench looks a lot more like a real
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system environment.
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To Do: Add back "random" wait state generation for RAM access.
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Updates to User Guide -- Minor corrections to instruction set details. Needs more
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review on condition code settings.
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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// SVN tag: None
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Jan 11,2010
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Jan 11,2010
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RTL - 85% done -- Fix error in Zero Flag caculation for ADC and SBC instructions
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RTL - 85% done -- Fix error in Zero Flag calculation for ADC and SBC instructions
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Fix Error in loading R2 durning cpu_state == BOOT_3.
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Fix Error in loading R2 durning cpu_state == BOOT_3.
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THere is a bug in DEBUG mode that is sensitive to number of preceding
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THere is a bug in DEBUG mode that is sensitive to number of preceding
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instructions and wait states that needs to be resolved.
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instructions and wait states that needs to be resolved.
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Updates to testbench --
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Updates to testbench --
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Nov 09,2009
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Nov 09,2009
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RTL - 85% done - Minor changes to Mastermode bus.
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RTL - 85% done - Minor changes to Mastermode bus.
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Updates to testbench, Moved RAM.to submodule, Added bus arbitration module
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Updates to testbench, Moved RAM.to submodule, Added bus arbitration module
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but this is not fully functional. Causes timing problems when master is
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but this is not fully functional. Causes timing problems when master is
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polling xgate registers durning debug mode tests. Will probably change RAM
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polling Xgate registers durning debug mode tests. Will probably change RAM
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model to dual port in next revision.
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model to dual port in next revision.
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Updated master module to include WISHBONE select inputs.
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Updated master module to include WISHBONE select inputs.
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Updates to User Guide.
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Updates to User Guide.
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