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// 45678901234567890123456789012345678901234567890123456789012345678901234567890
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// 45678901234567890123456789012345678901234567890123456789012345678901234567890
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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// SVN tag: None
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// SVN tag: None
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Feb 12,2010
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RTL - Update to the WISHBONE interface when wait states are enabled to trade
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16 data flops for 5 address registers. This change now also requires single
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cycle timing on the WISHBONE address bus, multi-cycle timing is still
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allowed on the WISHBONE write data bus. In the old design WISHBONE read
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cycles required the address to be decoded and the read data to be latched
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in the first cycle and the there was a whole cycle to drive the read data
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bus. The new design latches the address in the first cycle then decodes the
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address and outputs the data in the second cycle. (The WISHBONE bus doesn't
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require the address or data to be latched for multi-cycle operation but by
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doing this it is hoped some power will be saved in the combinational logic
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by reducing the decoding activity at each address change.)
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Testbench - No change.
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Doc - No change.
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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// SVN tag: None
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Jan 27,2010
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Jan 27,2010
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RTL - 85% done -- Fixed error in wbs_ack_o signal when Xgate wait states were
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RTL - 85% done -- Fixed error in wbs_ack_o signal when Xgate wait states were
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enabled. If a slave bus transaction was started but not completed in the
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enabled. If a slave bus transaction was started but not completed in the
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second cycle a wbs_ack_o output was still generated. Added a wbs_err_o output
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second cycle a wbs_ack_o output was still generated. Added a wbs_err_o output
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signal to flag this input condition but not sure if it is really needed.
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signal to flag this input condition but not sure if it is really needed.
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