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[/] [xgate/] [trunk/] [README.txt] - Diff between revs 58 and 61
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// 45678901234567890123456789012345678901234567890123456789012345678901234567890
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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// SVN tag: None
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// SVN tag: None
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Apr 5,2010
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RTL - First pass at fixing bug when entering DEBUG by command from the slave
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WISHBONE bus. All tests now pass when the RAM wait states are set to zero,
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although there are errors in DEBUG mode when RAM wait states are increased.
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Icarus Verilog version 0.9.2 now supports the "generate" command. This is
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now used to instantiate the semaphore registers.
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Testbench - Added capability to insert wait states on RAM access.
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Doc - No change.
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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// SVN tag: None
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Feb 12,2010
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Feb 12,2010
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RTL - Update to the WISHBONE interface when wait states are enabled to trade
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RTL - Update to the WISHBONE interface when wait states are enabled to trade
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16 data flops for 5 address registers. This change now also requires single
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16 data flops for 5 address registers. This change now also requires single
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cycle timing on the WISHBONE address bus, multi-cycle timing is still
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cycle timing on the WISHBONE address bus, multi-cycle timing is still
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allowed on the WISHBONE write data bus. In the old design WISHBONE read
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allowed on the WISHBONE write data bus. In the old design WISHBONE read
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