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[/] [xgate/] [trunk/] [README.txt] - Diff between revs 61 and 66
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// 45678901234567890123456789012345678901234567890123456789012345678901234567890
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// 45678901234567890123456789012345678901234567890123456789012345678901234567890
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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// SVN tag: None
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// SVN tag: None
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Apr 22,2010
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RTL - Fixed bug when entering DEBUG by command from the slave WISHBONE bus.
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All tests now pass when the RAM wait states are set from zero to four. Five
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wait states times out in simulation while running the last test which is
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a simple register test otherwise I expect it would pass.
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Testbench - Many of the failures while testing wait states were due to fixed
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delays coded in the testbench. As necessary delays were changed to be a
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function of a parameter that is based on the number of RAM wait states.
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Doc - No change.
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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// SVN tag: None
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Apr 5,2010
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Apr 5,2010
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RTL - First pass at fixing bug when entering DEBUG by command from the slave
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RTL - First pass at fixing bug when entering DEBUG by command from the slave
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WISHBONE bus. All tests now pass when the RAM wait states are set to zero,
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WISHBONE bus. All tests now pass when the RAM wait states are set to zero,
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although there are errors in DEBUG mode when RAM wait states are increased.
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although there are errors in DEBUG mode when RAM wait states are increased.
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Icarus Verilog version 0.9.2 now supports the "generate" command. This is
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Icarus Verilog version 0.9.2 now supports the "generate" command. This is
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