URL
https://opencores.org/ocsvn/xgate/xgate/trunk
[/] [xgate/] [trunk/] [README.txt] - Diff between revs 66 and 71
Go to most recent revision |
Show entire file |
Details |
Blame |
View Log
| Rev 66 |
Rev 71 |
| Line 1... |
Line 1... |
// 45678901234567890123456789012345678901234567890123456789012345678901234567890
|
// 45678901234567890123456789012345678901234567890123456789012345678901234567890
|
////////////////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////////////////
|
// SVN tag: None
|
// SVN tag: None
|
|
|
|
May 12,2010
|
|
RTL - Added new control registers for interrupt bypass function. Out of reset
|
|
all input interrupts are bypassed directly to the Xgate interrupt outputs.
|
|
The interrupts are also disabled from effecting the Xgate till the bypass
|
|
is disabled. The interrupt priority has been flipped so that now the lowest
|
|
index input interrupt has the highest priority.
|
|
|
|
Testbench - Added semaphore register and read only registers to observe irq
|
|
outputs of Xgate to testbench slave module. Added parameters to support new
|
|
Xgate registers and testbench registers. Added new test to checkout
|
|
bypass functionality and interrupt priority encoding.
|
|
|
|
Doc - Updated with additions of IRQ Bypass registers.
|
|
|
|
////////////////////////////////////////////////////////////////////////////////
|
|
////////////////////////////////////////////////////////////////////////////////
|
|
// SVN tag: None
|
|
|
Apr 22,2010
|
Apr 22,2010
|
RTL - Fixed bug when entering DEBUG by command from the slave WISHBONE bus.
|
RTL - Fixed bug when entering DEBUG by command from the slave WISHBONE bus.
|
All tests now pass when the RAM wait states are set from zero to four. Five
|
All tests now pass when the RAM wait states are set from zero to four. Five
|
wait states times out in simulation while running the last test which is
|
wait states times out in simulation while running the last test which is
|
a simple register test otherwise I expect it would pass.
|
a simple register test otherwise I expect it would pass.
|
© copyright 1999-2024
OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.