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// 45678901234567890123456789012345678901234567890123456789012345678901234567890
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// 45678901234567890123456789012345678901234567890123456789012345678901234567890
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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// SVN tag: None
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// SVN tag: None
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August 11,2010
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RTL - No Change
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Applications - Added the "application" directory to the "sw" directory. The
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first application code added is the SKIPJACK encrypt/decrypt function. This
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algorithm works on a 64 bit block of data and uses an 80 bit key. See the
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"sw/applications/skipjack/README.txt" file for more information.
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Testbench - To aid in software development a simple debug module was added to
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the testbench. The debugger loads watchpoint addresses stored in RAM after
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the first RAM initialization. The debugger generates trigger signals that
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can be watched in the waveform viewer and captures a copy of the CPU
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registers at each trigger event. The watch point addresses are captured by
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the assembler and stored in RAM addresses reserved for the test bench.
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There are enable registers in the testbench that can enable or disable any
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of the eight individual watchpoints under testbench control.
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Doc - Made corrections to some of the example code in the detailed instruction
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descriptions.
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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// SVN tag: None
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June 10,2010
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June 10,2010
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RTL - No Change
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RTL - No Change
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Testbench - No Change.
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Testbench - No Change.
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Line 163... |
// SVN tag: None
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// SVN tag: None
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Jan 11,2010
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Jan 11,2010
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RTL - 85% done -- Fix error in Zero Flag calculation for ADC and SBC instructions
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RTL - 85% done -- Fix error in Zero Flag calculation for ADC and SBC instructions
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Fix Error in loading R2 durning cpu_state == BOOT_3.
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Fix Error in loading R2 durning cpu_state == BOOT_3.
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THere is a bug in DEBUG mode that is sensitive to number of preceding
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There is a bug in DEBUG mode that is sensitive to number of preceding
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instructions and wait states that needs to be resolved.
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instructions and wait states that needs to be resolved.
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Updates to testbench --
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Updates to testbench --
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Updates to User Guide -- First pass with instruction set details. Needs more
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Updates to User Guide -- First pass with instruction set details. Needs more
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