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[/] [xgate/] [trunk/] [bench/] [verilog/] [tst_bench_top.v] - Diff between revs 11 and 21

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Rev 11 Rev 21
Line 43... Line 43... 
 
 
 
 
module tst_bench_top();
 
module tst_bench_top();
 
 
 
 
 
  parameter MAX_CHANNEL = 127;    // Max XGATE Interrupt Channel Number
 
  parameter MAX_CHANNEL = 127;    // Max XGATE Interrupt Channel Number
 
  parameter STOP_ON_ERROR = 1'b0;
 
  parameter STOP_ON_ERROR = 1'b0;
 
  parameter MAX_VECTOR = 1800;
 
  parameter MAX_VECTOR = 2100;
 
 
 
 
 
  //
 
  //
 
  // wires && regs
 
  // wires && regs
 
  //
 
  //
 
  reg        mstr_test_clk;
 
  reg        mstr_test_clk;
Line 75... Line 75... 
  wire count_en_1;
 
  wire count_en_1;
 
  wire count_flag_1;
 
  wire count_flag_1;
 
 
 
 
 
  reg [15:0] q, qq;
 
  reg [15:0] q, qq;
 
 
 
 
 
  reg  [  7:0] ram_8 [65535:0];
 
  reg  [  7:0] ram_8 [65535:0];      // Testbench memory for holding XGATE test code
 
  wire         write_mem_strb_l;
 
  wire         write_mem_strb_l;
 
  wire         write_mem_strb_h;
 
  wire         write_mem_strb_h;
 
  reg  [127:0] channel_req;
 
  reg  [MAX_CHANNEL:0] channel_req;  // XGATE Interrupt inputs
 
  wire [  7:0] xgswt;        // XGATE Software Triggers
 
  wire [MAX_CHANNEL:0] xgif;         // XGATE Interrupt outputs
 
  wire [MAX_CHANNEL:0] xgif; // Max XGATE Interrupt Channel Number
 
  wire         [  7:0] xgswt;        // XGATE Software Trigger outputs
 
  wire         xg_sw_irq;    // Xgate Software interrupt
 
  wire                 xg_sw_irq;    // Xgate Software Error interrupt
 
 
 
 
 
 
 
 
 
  wire [15:0] xgate_address;
 
  wire [15:0] wbm_dat_o;         // WISHBONE Master Mode data output from XGATE
 
  wire [15:0] write_mem_data;
 
  wire [15:0] wbm_dat_i;         // WISHBONE Master Mode data input to XGATE
 
  wire [15:0] read_mem_data;
 
  wire [15:0] wbm_adr_o;         // WISHBONE Master Mode address output from XGATE
 
 
 
 
 
  wire [15:0] wbm_dat_o;
 
 
 
  wire [15:0] wbm_dat_i;
 
 
 
  wire [15:0] wbm_adr_o;
 
 
 
  wire [ 1:0] wbm_sel_o;
 
  wire [ 1:0] wbm_sel_o;
 
 
 
 
 
 
 
 
 
  // Name Address Locations
 
  // Name Address Locations
 
  parameter XGATE_XGMCTL   = 5'h00;
 
  parameter XGATE_XGMCTL   = 5'h00;
Line 113... Line 109... 
  parameter XGATE_XGSWT    = 5'h0d;
 
  parameter XGATE_XGSWT    = 5'h0d;
 
  parameter XGATE_XGSEM    = 5'h0e;
 
  parameter XGATE_XGSEM    = 5'h0e;
 
  parameter XGATE_RES1     = 5'h0f;
 
  parameter XGATE_RES1     = 5'h0f;
 
  parameter XGATE_XGCCR    = 5'h10;
 
  parameter XGATE_XGCCR    = 5'h10;
 
  parameter XGATE_XGPC     = 5'h11;
 
  parameter XGATE_XGPC     = 5'h11;
 
  parameter XGATE_RES1     = 5'h12;
 
  parameter XGATE_RES2     = 5'h12;
 
  parameter XGATE_XGR1     = 5'h13;
 
  parameter XGATE_XGR1     = 5'h13;
 
  parameter XGATE_XGR2     = 5'h14;
 
  parameter XGATE_XGR2     = 5'h14;
 
  parameter XGATE_XGR3     = 5'h15;
 
  parameter XGATE_XGR3     = 5'h15;
 
  parameter XGATE_XGR4     = 5'h16;
 
  parameter XGATE_XGR4     = 5'h16;
 
  parameter XGATE_XGR5     = 5'h17;
 
  parameter XGATE_XGR5     = 5'h17;
Line 140... Line 136... 
  parameter XGMCTL_XGFACT   = 15'h0008;
 
  parameter XGMCTL_XGFACT   = 15'h0008;
 
  parameter XGMCTL_XGBRKIE  = 15'h0004;
 
  parameter XGMCTL_XGBRKIE  = 15'h0004;
 
  parameter XGMCTL_XGSWEIF  = 15'h0002;
 
  parameter XGMCTL_XGSWEIF  = 15'h0002;
 
  parameter XGMCTL_XGIE     = 15'h0001;
 
  parameter XGMCTL_XGIE     = 15'h0001;
 
 
 
 
 
  parameter COP_CNTRL = 5'b0_0000;
 
 
 
 
 
 
 
  parameter COP_CNTRL_COP_EVENT  = 16'h0100;  // COP Enable interrupt request
 
 
 
 
 
 
 
  parameter CHECK_POINT = 16'h8000;
 
  parameter CHECK_POINT = 16'h8000;
 
  parameter CHANNEL_ACK = CHECK_POINT + 2;
 
  parameter CHANNEL_ACK = CHECK_POINT + 2;
 
  parameter CHANNEL_ERR = CHECK_POINT + 4;
 
  parameter CHANNEL_ERR = CHECK_POINT + 4;
 
  reg [ 7:0] check_point_reg;
 
  reg [ 7:0] check_point_reg;
Line 207... Line 200... 
  always @(posedge mstr_test_clk)
 
  always @(posedge mstr_test_clk)
 
    begin
 
    begin
 
      vector <= vector + 1;
 
      vector <= vector + 1;
 
      if (vector > MAX_VECTOR)
 
      if (vector > MAX_VECTOR)
 
        begin
 
        begin
 
          error_count = error_count + 1;
 
          error_count <= error_count + 1;
 
          $display("\n ------ !!!!! Simulation Timeout at vector=%d\n -------", vector);
 
          $display("\n ------ !!!!! Simulation Timeout at vector=%d\n -------", vector);
 
          wrap_up;
 
          wrap_up;
 
        end
 
        end
 
    end
 
    end
 
 
 
 
 
 
 
  // Add up errors tha come from WISHBONE read compares
 
 
 
  always @u0.cmp_error_detect
 
 
 
    begin
 
 
 
      error_count <= error_count + 1;
 
 
 
    end
 
 
 
 
 
 
 
 
 
  // Throw in some wait states from the memory
 
  // Throw in some wait states from the memory
 
  always @(posedge mstr_test_clk)
 
  always @(posedge mstr_test_clk)
 
    if (((vector % 5) == 0) && (xgate.risc.load_next_inst || xgate.risc.data_access))
 
    if (((vector % 5) == 0) && (xgate.risc.load_next_inst || xgate.risc.data_access))
 
//    if ((vector % 5) == 0)
 
//    if ((vector % 5) == 0)
Line 227... Line 226... 
 
 
 
 
  // Write memory interface to RAM
 
  // Write memory interface to RAM
 
  always @(posedge mstr_test_clk)
 
  always @(posedge mstr_test_clk)
 
    begin
 
    begin
 
      if (write_mem_strb_l && !write_mem_strb_h && wbm_ack_i)
 
      if (write_mem_strb_l && !write_mem_strb_h && wbm_ack_i)
 
        ram_8[xgate_address] <= write_mem_data[7:0];
 
        ram_8[wbm_adr_o] <= wbm_dat_o[7:0];
 
      if (write_mem_strb_h && !write_mem_strb_l && wbm_ack_i)
 
      if (write_mem_strb_h && !write_mem_strb_l && wbm_ack_i)
 
        ram_8[xgate_address] <= write_mem_data[7:0];
 
        ram_8[wbm_adr_o] <= wbm_dat_o[7:0];
 
      if (write_mem_strb_h && write_mem_strb_l && wbm_ack_i)
 
      if (write_mem_strb_h && write_mem_strb_l && wbm_ack_i)
 
        begin
 
        begin
 
          ram_8[xgate_address]   <= write_mem_data[15:8];
 
          ram_8[wbm_adr_o]   <= wbm_dat_o[15:8];
 
          ram_8[xgate_address+1] <= write_mem_data[7:0];
 
          ram_8[wbm_adr_o+1] <= wbm_dat_o[7:0];
 
        end
 
        end
 
    end
 
    end
 
 
 
 
 
  // Special Memory Mapped Testbench Registers
 
  // Special Memory Mapped Testbench Registers
 
  always @(posedge mstr_test_clk or negedge rstn)
 
  always @(posedge mstr_test_clk or negedge rstn)
Line 246... Line 245... 
        begin
 
        begin
 
          check_point_reg <= 0;
 
          check_point_reg <= 0;
 
          channel_ack_reg <= 0;
 
          channel_ack_reg <= 0;
 
          channel_err_reg <= 0;
 
          channel_err_reg <= 0;
 
        end
 
        end
 
      if (write_mem_strb_l && wbm_ack_i && (xgate_address == CHECK_POINT))
 
      if (write_mem_strb_l && wbm_ack_i && (wbm_adr_o == CHECK_POINT))
 
        begin
 
        begin
 
          check_point_reg <= write_mem_data[7:0];
 
          check_point_reg <= wbm_dat_o[7:0];
 
          #1;
 
          #1;
 
          -> check_point_wrt;
 
          -> check_point_wrt;
 
        end
 
        end
 
      if (write_mem_strb_l && wbm_ack_i && (xgate_address == CHANNEL_ACK))
 
      if (write_mem_strb_l && wbm_ack_i && (wbm_adr_o == CHANNEL_ACK))
 
        begin
 
        begin
 
          channel_ack_reg <= write_mem_data[7:0];
 
          channel_ack_reg <= wbm_dat_o[7:0];
 
          #1;
 
          #1;
 
          -> channel_ack_wrt;
 
          -> channel_ack_wrt;
 
        end
 
        end
 
      if (write_mem_strb_l && wbm_ack_i && (xgate_address == CHANNEL_ERR))
 
      if (write_mem_strb_l && wbm_ack_i && (wbm_adr_o == CHANNEL_ERR))
 
        begin
 
        begin
 
          channel_err_reg <= write_mem_data[7:0];
 
          channel_err_reg <= wbm_dat_o[7:0];
 
          #1;
 
          #1;
 
          -> channel_err_wrt;
 
          -> channel_err_wrt;
 
        end
 
        end
 
    end
 
    end
 
 
 
 
Line 285... Line 284... 
 
 
 
 
 
 
 
 
  // hookup wishbone master model
 
  // hookup wishbone master model
 
  wb_master_model #(.dwidth(16), .awidth(32))
 
  wb_master_model #(.dwidth(16), .awidth(32))
 
          u0 (
 
          u0 (
 
          .clk(mstr_test_clk),
 
          // Outputs
 
          .rst(rstn),
 
 
 
          .adr(adr),
 
 
 
          .din(dat_i),
 
 
 
          .dout(dat_o),
 
 
 
          .cyc(cyc),
 
          .cyc(cyc),
 
          .stb(stb),
 
          .stb(stb),
 
          .we(we),
 
          .we(we),
 
          .sel(),
 
          .sel(),
 
 
 
          .adr(adr),
 
 
 
          .dout(dat_o),
 
 
 
          // inputs
 
 
 
          .din(dat_i),
 
 
 
          .clk(mstr_test_clk),
 
          .ack(ack),
 
          .ack(ack),
 
 
 
          .rst(rstn),
 
          .err(1'b0),
 
          .err(1'b0),
 
          .rty(1'b0)
 
          .rty(1'b0)
 
  );
 
  );
 
 
 
 
 
 
 
 
Line 321... Line 322... 
                 ({16{stb2}} & dat2_i) |
 
                 ({16{stb2}} & dat2_i) |
 
                 ({16{stb3}} & {8'b0, dat3_i[7:0]});
 
                 ({16{stb3}} & {8'b0, dat3_i[7:0]});
 
 
 
 
 
  assign ack = ack_1 || ack_2 || ack_3 || ack_4;
 
  assign ack = ack_1 || ack_2 || ack_3 || ack_4;
 
 
 
 
 
  assign read_mem_data = {ram_8[xgate_address], ram_8[xgate_address+1]};
 
  assign wbm_dat_i = {ram_8[wbm_adr_o], ram_8[wbm_adr_o+1]};
 
 
 
 
 
  // hookup XGATE core - Parameters take all default values
 
  // hookup XGATE core - Parameters take all default values
 
  //  Async Reset, 16 bit Bus, 16 bit Granularity
 
  //  Async Reset, 16 bit Bus, 16 bit Granularity
 
  xgate_top  #(.SINGLE_CYCLE(1'b1),
 
  xgate_top  #(.SINGLE_CYCLE(1'b1),
 
               .MAX_CHANNEL(MAX_CHANNEL))    // Max XGATE Interrupt Channel Number
 
               .MAX_CHANNEL(MAX_CHANNEL))    // Max XGATE Interrupt Channel Number
Line 342... Line 343... 
          .wbs_cyc_i( cyc ),
 
          .wbs_cyc_i( cyc ),
 
          .wbs_sel_i( 2'b11 ),
 
          .wbs_sel_i( 2'b11 ),
 
          .wbs_ack_o( ack_1 ),
 
          .wbs_ack_o( ack_1 ),
 
 
 
 
 
          // Wishbone master Signals
 
          // Wishbone master Signals
 
          .wbm_dat_o( write_mem_data ),
 
          .wbm_dat_o( wbm_dat_o ),
 
          .wbm_we_o( wbm_we_o ),
 
          .wbm_we_o( wbm_we_o ),
 
          .wbm_stb_o( wbm_stb_o ),
 
          .wbm_stb_o( wbm_stb_o ),
 
          .wbm_cyc_o( wbm_cyc_o ),
 
          .wbm_cyc_o( wbm_cyc_o ),
 
          .wbm_sel_o( wbm_sel_o ),
 
          .wbm_sel_o( wbm_sel_o ),
 
          .wbm_adr_o( xgate_address ),
 
          .wbm_adr_o( wbm_adr_o ),
 
          .wbm_dat_i( read_mem_data ),
 
          .wbm_dat_i( wbm_dat_i ),
 
          .wbm_ack_i( wbm_ack_i ),
 
          .wbm_ack_i( wbm_ack_i ),
 
 
 
 
 
          .xgif( xgif ),             // XGATE Interrupt Flag
 
          .xgif( xgif ),             // XGATE Interrupt Flag output
 
          .xg_sw_irq( xg_sw_irq ),
 
          .xg_sw_irq( xg_sw_irq ),   // XGATE Software Error Interrupt Flag output
 
          .risc_clk( mstr_test_clk ),
 
 
 
          .xgswt( xgswt ),
 
          .xgswt( xgswt ),
 
          .chan_req_i( {channel_req[127:40], xgswt, channel_req[31:0]} ),
 
          .risc_clk( mstr_test_clk ),
 
 
 
          .chan_req_i( {channel_req[MAX_CHANNEL:40], xgswt, channel_req[31:0]} ),
 
          .write_mem_strb_l( write_mem_strb_l ),
 
          .write_mem_strb_l( write_mem_strb_l ),
 
          .write_mem_strb_h( write_mem_strb_h ),
 
          .write_mem_strb_h( write_mem_strb_h ),
 
          .scantestmode( scantestmode )
 
          .scantestmode( scantestmode )
 
  );
 
  );
 
 
 
 
Line 370... Line 371... 
////////////////////////////////////////////////////////////////////////////////
 
////////////////////////////////////////////////////////////////////////////////
 
 
 
 
 
// Test Program
 
// Test Program
 
initial
 
initial
 
  begin
 
  begin
 
      $readmemh("../../../bench/verilog/inst_test.v", ram_8);
 
 
 
      $display("\nstatus at time: %t Testbench started", $time);
 
      $display("\nstatus at time: %t Testbench started", $time);
 
 
 
 
 
      // reset system
 
      // reset system
 
      rstn = 1'b1; // negate reset
 
      rstn = 1'b1; // negate reset
 
      channel_req = 1; // 
      channel_req = 1; //
Line 394... Line 394... 
 
 
 
 
      test_inst_set;
 
      test_inst_set;
 
 
 
 
 
      test_debug_mode;
 
      test_debug_mode;
 
 
 
 
 
//      test_debug_bit; 
      test_debug_bit;
 
 
 
 
 
 
 
      test_chid_debug;
 
 
 
 
 
      wrap_up;
 
      wrap_up;
 
      //
 
      //
 
      // program core
 
      // program core
 
      //
 
      //
Line 408... Line 410... 
      repeat(10) @(posedge mstr_test_clk);
 
      repeat(10) @(posedge mstr_test_clk);
 
 
 
 
 
      wrap_up;
 
      wrap_up;
 
  end
 
  end
 
 
 
 
 
 
 
// Test CHID Debug mode operation
 
 
 
task test_chid_debug;
 
 
 
  begin
 
 
 
    test_num = test_num + 1;
 
 
 
    $display("\nTEST #%d Starts at vector=%d, test_chid_debug", test_num, vector);
 
 
 
    $readmemh("../../../bench/verilog/debug_test.v", ram_8);
 
 
 
 
 
 
 
    data_xgmctl = XGMCTL_XGBRKIEM | XGMCTL_XGBRKIE;
 
 
 
    u0.wb_write(0, XGATE_XGMCTL, data_xgmctl);   // Enable interrupt on BRK instruction
 
 
 
 
 
 
 
    activate_thread_sw(3);
 
 
 
 
 
 
 
    wait_debug_set;   // Debug Status bit is set by BRK instruction
 
 
 
 
 
 
 
    u0.wb_cmp(0, XGATE_XGPC,     16'h20c6);      // See Program code (BRK).
 
 
 
    u0.wb_cmp(0, XGATE_XGR3,     16'h0001);      // See Program code.R3 = 1
 
 
 
    u0.wb_cmp(0, XGATE_XGCHID,   16'h0003);      // Check for Correct CHID
 
 
 
 
 
 
 
    channel_req[5] = 1'b1; //
 
 
 
    repeat(7) @(posedge mstr_test_clk);
 
 
 
    u0.wb_cmp(0, XGATE_XGCHID,   16'h0003);      // Check for Correct CHID
 
 
 
 
 
 
 
    u0.wb_write(0, XGATE_XGCHID, 16'h000f);      // Change CHID
 
 
 
    u0.wb_cmp(0, XGATE_XGCHID,   16'h000f);      // Check for Correct CHID
 
 
 
 
 
 
 
    u0.wb_write(0, XGATE_XGCHID, 16'h0000);      // Change CHID to 00, RISC should go to IDLE state
 
 
 
 
 
 
 
    repeat(1) @(posedge mstr_test_clk);
 
 
 
 
 
 
 
    u0.wb_write(0, XGATE_XGCHID, 16'h0004);      // Change CHID
 
 
 
 
 
 
 
    repeat(8) @(posedge mstr_test_clk);
 
 
 
 
 
 
 
    data_xgmctl = XGMCTL_XGDBGM;
 
 
 
    u0.wb_write(0, XGATE_XGMCTL, data_xgmctl);   // Clear Debug Mode Control Bit
 
 
 
 
 
 
 
    wait_debug_set;   // Debug Status bit is set by BRK instruction
 
 
 
    u0.wb_cmp(0, XGATE_XGCHID,   16'h0004);      // Check for Correct CHID
 
 
 
    u0.wb_write(0, XGATE_XGMCTL, data_xgmctl);   // Clear Debug Mode Control Bit (Excape from Break State and run)
 
 
 
 
 
 
 
    wait_debug_set;   // Debug Status bit is set by BRK instruction
 
 
 
    u0.wb_cmp(0, XGATE_XGCHID,   16'h0005);      // Check for Correct CHID
 
 
 
    activate_channel(6);
 
 
 
    u0.wb_write(0, XGATE_XGMCTL, data_xgmctl);   // Clear Debug Mode Control Bit (Excape from Break State and run)
 
 
 
 
 
 
 
    wait_debug_set;   // Debug Status bit is set by BRK instruction
 
 
 
    u0.wb_cmp(0, XGATE_XGCHID,   16'h0006);      // Check for Correct CHID
 
 
 
    u0.wb_cmp(0, XGATE_XGPC,     16'h211c);      // See Program code (BRK)
 
 
 
    data_xgmctl = XGMCTL_XGSSM | XGMCTL_XGSS;
 
 
 
    u0.wb_write(0, XGATE_XGMCTL, data_xgmctl);   // Do a Single Step
 
 
 
    repeat(8) @(posedge mstr_test_clk);
 
 
 
    u0.wb_cmp(0, XGATE_XGPC,     16'h211e);      // See Program code (BRA)
 
 
 
    u0.wb_write(0, XGATE_XGMCTL, data_xgmctl);   // Do a Single Step
 
 
 
    repeat(8) @(posedge mstr_test_clk);
 
 
 
    u0.wb_cmp(0, XGATE_XGPC,     16'h2122);      // See Program code ()
 
 
 
 
 
 
 
    repeat(20) @(posedge mstr_test_clk);
 
 
 
 
 
 
 
    data_xgmctl = XGMCTL_XGDBGM;
 
 
 
    u0.wb_write(0, XGATE_XGMCTL, data_xgmctl);   // Clear Debug Mode Control Bit
 
 
 
 
 
 
 
    repeat(50) @(posedge mstr_test_clk);
 
 
 
 
 
 
 
  end
 
 
 
endtask
 
 
 
 
 
// Test Debug bit operation
 
// Test Debug bit operation
 
task test_debug_bit;
 
task test_debug_bit;
 
  begin
 
  begin
 
    test_num = test_num + 1;
 
    test_num = test_num + 1;
 
    $display("\nTEST #%d Starts at vector=%d, test_debug_mode", test_num, vector);
 
    $display("\nTEST #%d Starts at vector=%d, test_debug_bit", test_num, vector);
 
    $readmemh("../../../bench/verilog/debug_test.v", ram_8);
 
    $readmemh("../../../bench/verilog/debug_test.v", ram_8);
 
 
 
 
 
    data_xgmctl = XGMCTL_XGBRKIEM | XGMCTL_XGBRKIE;
 
    data_xgmctl = XGMCTL_XGBRKIEM | XGMCTL_XGBRKIE;
 
    u0.wb_write(0, XGATE_XGMCTL, data_xgmctl);   // Enable interrupt on BRK instruction
 
    u0.wb_write(0, XGATE_XGMCTL, data_xgmctl);   // Enable interrupt on BRK instruction
 
 
 
 
Line 424... Line 492... 
 
 
 
 
    repeat(25) @(posedge mstr_test_clk);
 
    repeat(25) @(posedge mstr_test_clk);
 
 
 
 
 
    data_xgmctl = XGMCTL_XGDBGM | XGMCTL_XGDBG;
 
    data_xgmctl = XGMCTL_XGDBGM | XGMCTL_XGDBG;
 
    u0.wb_write(0, XGATE_XGMCTL, data_xgmctl);   // Set Debug Mode Control Bit
 
    u0.wb_write(0, XGATE_XGMCTL, data_xgmctl);   // Set Debug Mode Control Bit
 
//    data_xgmctl = XGMCTL_XGDBGM;
 
    repeat(5) @(posedge mstr_test_clk);
 
//    u0.wb_write(0, XGATE_XGMCTL, data_xgmctl);   // Clear Debug Mode Control Bit
 
 
 
 
 
    u0.wb_read(1, XGATE_XGR3, q);
 
 
 
    data_xgmctl = XGMCTL_XGSSM | XGMCTL_XGSS;
 
 
 
    qq = q;
 
 
 
 
 
 
 
    // The Xgate test program is in an infinate loop incrementing R3
 
 
 
    while (qq == q)  // Look for change in R3 register
 
 
 
      begin
 
 
 
        u0.wb_write(0, XGATE_XGMCTL, data_xgmctl);   // Do a Single Step
 
 
 
        repeat(5) @(posedge mstr_test_clk);
 
 
 
        u0.wb_read(1, XGATE_XGR3, q);
 
 
 
      end
 
 
 
    if (q != (qq+1))
 
 
 
      begin
 
 
 
        $display("Error! - Unexpected value of R3 at vector=%d", vector);
 
 
 
        error_count = error_count + 1;
 
 
 
      end
 
 
 
 
 
 
 
 
 
 
 
    u0.wb_write(1, XGATE_XGPC, 16'h2094);        // Write to PC to force exit from infinate loop
 
 
 
    repeat(5) @(posedge mstr_test_clk);
 
 
 
 
 
 
 
    data_xgmctl = XGMCTL_XGSSM | XGMCTL_XGSS;
 
 
 
    u0.wb_write(0, XGATE_XGMCTL, data_xgmctl);   // Do a Single Step (Load ADDL instruction)
 
 
 
    repeat(5) @(posedge mstr_test_clk);
 
 
 
    u0.wb_cmp(0, XGATE_XGR4,     16'h0002);      // See Program code.(R4 <= R4 + 1)
 
 
 
 
 
 
 
    u0.wb_write(0, XGATE_XGMCTL, data_xgmctl);   // Do a Single Step (Load ADDL instruction)
 
 
 
    repeat(5) @(posedge mstr_test_clk);
 
 
 
    u0.wb_cmp(0, XGATE_XGR4,     16'h0003);      // See Program code.(R4 <= R4 + 1)
 
 
 
 
 
 
 
    data_xgmctl = XGMCTL_XGDBGM;
 
 
 
    u0.wb_write(0, XGATE_XGMCTL, data_xgmctl);   // Clear Debug Mode Control Bit
 
                                                 // Should be back in Run Mode
 
                                                 // Should be back in Run Mode
 
    wait_irq_set(1);
 
 
 
    u0.wb_write(1, XGATE_XGIF_0, 16'h0004);
 
 
 
 
 
 
 
    data_xgmctl = XGMCTL_XGSWEIFM | XGMCTL_XGSWEIF | XGMCTL_XGBRKIEM;
 
//    data_xgmctl = XGMCTL_XGSWEIFM | XGMCTL_XGSWEIF | XGMCTL_XGBRKIEM;
 
    u0.wb_write(0, XGATE_XGMCTL, data_xgmctl);   // Clear Software Interrupt and BRK Interrupt Enable Bit
 
//    u0.wb_write(0, XGATE_XGMCTL, data_xgmctl);   // Clear Software Interrupt and BRK Interrupt Enable Bit
 
    repeat(15) @(posedge mstr_test_clk);
 
    repeat(15) @(posedge mstr_test_clk);
 
 
 
 
 
  end
 
  end
 
endtask
 
endtask
 
 
 
 
Line 504... Line 602... 
    repeat(5) @(posedge mstr_test_clk);
 
    repeat(5) @(posedge mstr_test_clk);
 
    u0.wb_cmp(0, XGATE_XGPC,     16'h204c);      // PC + 2.
 
    u0.wb_cmp(0, XGATE_XGPC,     16'h204c);      // PC + 2.
 
 
 
 
 
    repeat(5) @(posedge mstr_test_clk);
 
    repeat(5) @(posedge mstr_test_clk);
 
 
 
 
 
    data_xgmctl = XGMCTL_XGDBGM | XGMCTL_XGDBG;
 
 
 
    u0.wb_write(0, XGATE_XGMCTL, data_xgmctl);   // Set Debug Mode Control Bit
 
 
 
    data_xgmctl = XGMCTL_XGDBGM;
 
    data_xgmctl = XGMCTL_XGDBGM;
 
    u0.wb_write(0, XGATE_XGMCTL, data_xgmctl);   // Clear Debug Mode Control Bit
 
    u0.wb_write(0, XGATE_XGMCTL, data_xgmctl);   // Clear Debug Mode Control Bit
 
                                                 // Should be back in Run Mode
 
                                                 // Should be back in Run Mode
 
    wait_irq_set(1);
 
    wait_irq_set(1);
 
    u0.wb_write(1, XGATE_XGIF_0, 16'h0002);
 
    u0.wb_write(1, XGATE_XGIF_0, 16'h0002);
Line 522... Line 618... 
endtask
 
endtask
 
 
 
 
 
// Test instruction set
 
// Test instruction set
 
task test_inst_set;
 
task test_inst_set;
 
  begin
 
  begin
 
 
 
    $readmemh("../../../bench/verilog/inst_test.v", ram_8);
 
    test_num = test_num + 1;
 
    test_num = test_num + 1;
 
    $display("\nTEST #%d Starts at vector=%d, inst_test", test_num, vector);
 
    $display("\nTEST #%d Starts at vector=%d, inst_test", test_num, vector);
 
 
 
    repeat(1) @(posedge mstr_test_clk);
 
 
 
 
 
    activate_thread_sw(1);
 
    activate_thread_sw(1);
 
    wait_irq_set(1);
 
    wait_irq_set(1);
 
    u0.wb_write(1, XGATE_XGIF_0, 16'h0002);
 
    u0.wb_write(1, XGATE_XGIF_0, 16'h0002);
 
 
 
 
Line 763... Line 861... 
  end
 
  end
 
endtask
 
endtask
 
 
 
 
 
task wrap_up;
 
task wrap_up;
 
  begin
 
  begin
 
 
 
    test_num = test_num + 1;
 
 
 
    repeat(10) @(posedge mstr_test_clk);
 
    $display("\nSimulation Finished!! - vector =%d", vector);
 
    $display("\nSimulation Finished!! - vector =%d", vector);
 
    if (error_count == 0)
 
    if (error_count == 0)
 
      $display("Simulation Passed");
 
      $display("Simulation Passed");
 
    else
 
    else
 
      $display("Simulation Failed");
 
      $display("Simulation Failed  --- Errors =%d", error_count);
 
 
 
 
 
    $finish;
 
    $finish;
 
  end
 
  end
 
endtask
 
endtask
 
 
 
 

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