| Line 43... |
Line 43... |
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module tst_bench_top();
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module tst_bench_top();
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parameter MAX_CHANNEL = 127; // Max XGATE Interrupt Channel Number
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parameter MAX_CHANNEL = 127; // Max XGATE Interrupt Channel Number
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parameter STOP_ON_ERROR = 1'b0;
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parameter STOP_ON_ERROR = 1'b0;
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parameter MAX_VECTOR = 2100;
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parameter MAX_VECTOR = 2200;
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//
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parameter L_BYTE = 2'bx1;
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// wires && regs
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parameter H_BYTE = 2'b1x;
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//
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parameter WORD = 2'b11;
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reg mstr_test_clk;
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reg [19:0] vector;
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reg [ 7:0] test_num;
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reg [15:0] wb_temp;
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reg rstn;
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reg sync_reset;
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reg por_reset_b;
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reg stop_mode;
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reg wait_mode;
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reg debug_mode;
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reg scantestmode;
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reg wbm_ack_i;
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wire [31:0] adr;
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wire [15:0] dat_i, dat_o, dat0_i, dat1_i, dat2_i, dat3_i;
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wire we;
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wire stb;
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wire cyc;
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wire ack, ack_1, ack_2, ack_3, ack_4;
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wire inta_1, inta_2, inta_3, inta_4;
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wire count_en_1;
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wire count_flag_1;
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reg [15:0] q, qq;
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reg [ 7:0] ram_8 [65535:0]; // Testbench memory for holding XGATE test code
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wire write_mem_strb_l;
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wire write_mem_strb_h;
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reg [MAX_CHANNEL:0] channel_req; // XGATE Interrupt inputs
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wire [MAX_CHANNEL:0] xgif; // XGATE Interrupt outputs
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wire [ 7:0] xgswt; // XGATE Software Trigger outputs
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wire xg_sw_irq; // Xgate Software Error interrupt
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wire [15:0] wbm_dat_o; // WISHBONE Master Mode data output from XGATE
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wire [15:0] wbm_dat_i; // WISHBONE Master Mode data input to XGATE
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wire [15:0] wbm_adr_o; // WISHBONE Master Mode address output from XGATE
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wire [ 1:0] wbm_sel_o;
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// Name Address Locations
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// Name Address Locations
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parameter XGATE_XGMCTL = 5'h00;
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parameter XGATE_BASE = 32'b0;
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parameter XGATE_XGCHID = 5'h01;
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parameter XGATE_XGMCTL = XGATE_BASE + 5'h00;
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parameter XGATE_XGISPHI = 5'h02;
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parameter XGATE_XGCHID = XGATE_BASE + 5'h01;
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parameter XGATE_XGISPLO = 5'h03;
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parameter XGATE_XGISPHI = XGATE_BASE + 5'h02;
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parameter XGATE_XGVBR = 5'h04;
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parameter XGATE_XGISPLO = XGATE_BASE + 5'h03;
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parameter XGATE_XGIF_7 = 5'h05;
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parameter XGATE_XGVBR = XGATE_BASE + 5'h04;
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parameter XGATE_XGIF_6 = 5'h06;
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parameter XGATE_XGIF_7 = XGATE_BASE + 5'h05;
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parameter XGATE_XGIF_5 = 5'h07;
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parameter XGATE_XGIF_6 = XGATE_BASE + 5'h06;
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parameter XGATE_XGIF_4 = 5'h08;
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parameter XGATE_XGIF_5 = XGATE_BASE + 5'h07;
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parameter XGATE_XGIF_3 = 5'h09;
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parameter XGATE_XGIF_4 = XGATE_BASE + 5'h08;
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parameter XGATE_XGIF_2 = 5'h0a;
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parameter XGATE_XGIF_3 = XGATE_BASE + 5'h09;
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parameter XGATE_XGIF_1 = 5'h0b;
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parameter XGATE_XGIF_2 = XGATE_BASE + 5'h0a;
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parameter XGATE_XGIF_0 = 5'h0c;
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parameter XGATE_XGIF_1 = XGATE_BASE + 5'h0b;
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parameter XGATE_XGSWT = 5'h0d;
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parameter XGATE_XGIF_0 = XGATE_BASE + 5'h0c;
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parameter XGATE_XGSEM = 5'h0e;
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parameter XGATE_XGSWT = XGATE_BASE + 5'h0d;
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parameter XGATE_RES1 = 5'h0f;
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parameter XGATE_XGSEM = XGATE_BASE + 5'h0e;
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parameter XGATE_XGCCR = 5'h10;
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parameter XGATE_RES1 = XGATE_BASE + 5'h0f;
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parameter XGATE_XGPC = 5'h11;
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parameter XGATE_XGCCR = XGATE_BASE + 5'h10;
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parameter XGATE_RES2 = 5'h12;
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parameter XGATE_XGPC = XGATE_BASE + 5'h11;
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parameter XGATE_XGR1 = 5'h13;
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parameter XGATE_RES2 = XGATE_BASE + 5'h12;
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parameter XGATE_XGR2 = 5'h14;
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parameter XGATE_XGR1 = XGATE_BASE + 5'h13;
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parameter XGATE_XGR3 = 5'h15;
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parameter XGATE_XGR2 = XGATE_BASE + 5'h14;
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parameter XGATE_XGR4 = 5'h16;
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parameter XGATE_XGR3 = XGATE_BASE + 5'h15;
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parameter XGATE_XGR5 = 5'h17;
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parameter XGATE_XGR4 = XGATE_BASE + 5'h16;
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parameter XGATE_XGR6 = 5'h18;
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parameter XGATE_XGR5 = XGATE_BASE + 5'h17;
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parameter XGATE_XGR7 = 5'h19;
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parameter XGATE_XGR6 = XGATE_BASE + 5'h18;
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parameter XGATE_XGR7 = XGATE_BASE + 5'h19;
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// Define bits in XGATE Control Register
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// Define bits in XGATE Control Register
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parameter XGMCTL_XGEM = 16'h8000;
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parameter XGMCTL_XGEM = 16'h8000;
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parameter XGMCTL_XGFRZM = 16'h4000;
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parameter XGMCTL_XGFRZM = 16'h4000;
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parameter XGMCTL_XGDBGM = 15'h2000;
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parameter XGMCTL_XGDBGM = 15'h2000;
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| Line 136... |
Line 97... |
parameter XGMCTL_XGFACT = 15'h0008;
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parameter XGMCTL_XGFACT = 15'h0008;
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parameter XGMCTL_XGBRKIE = 15'h0004;
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parameter XGMCTL_XGBRKIE = 15'h0004;
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parameter XGMCTL_XGSWEIF = 15'h0002;
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parameter XGMCTL_XGSWEIF = 15'h0002;
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parameter XGMCTL_XGIE = 15'h0001;
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parameter XGMCTL_XGIE = 15'h0001;
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parameter CHECK_POINT = 16'h8000;
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parameter CHECK_POINT = 16'h8000;
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parameter CHANNEL_ACK = CHECK_POINT + 2;
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parameter CHANNEL_ACK = CHECK_POINT + 2;
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parameter CHANNEL_ERR = CHECK_POINT + 4;
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parameter CHANNEL_ERR = CHECK_POINT + 4;
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parameter SYS_RAM_BASE = 32'h0002_0000;
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//
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// wires && regs
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//
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reg mstr_test_clk;
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reg [19:0] vector;
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reg [15:0] error_count;
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reg [ 7:0] test_num;
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reg [15:0] q, qq;
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reg [ 7:0] check_point_reg;
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reg [ 7:0] check_point_reg;
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reg [ 7:0] channel_ack_reg;
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reg [ 7:0] channel_ack_reg;
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reg [ 7:0] channel_err_reg;
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reg [ 7:0] channel_err_reg;
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event check_point_wrt;
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event check_point_wrt;
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event channel_ack_wrt;
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event channel_ack_wrt;
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event channel_err_wrt;
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event channel_err_wrt;
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reg [15:0] error_count;
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reg rstn;
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reg sync_reset;
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reg por_reset_b;
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reg stop_mode;
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reg wait_mode;
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reg debug_mode;
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reg scantestmode;
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reg wbm_ack_i;
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wire [15:0] dat_i, dat1_i, dat2_i, dat3_i;
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wire ack, ack_2, ack_3, ack_4;
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reg [MAX_CHANNEL:0] channel_req; // XGATE Interrupt inputs
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wire [MAX_CHANNEL:0] xgif; // XGATE Interrupt outputs
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wire [ 7:0] xgswt; // XGATE Software Trigger outputs
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wire xg_sw_irq; // Xgate Software Error interrupt
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wire [15:0] wbm_dat_o; // WISHBONE Master Mode data output from XGATE
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wire [15:0] wbm_dat_i; // WISHBONE Master Mode data input to XGATE
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wire [15:0] wbm_adr_o; // WISHBONE Master Mode address output from XGATE
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wire [ 1:0] wbm_sel_o;
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reg mem_wait_state_enable;
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reg mem_wait_state_enable;
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wire [15:0] tb_ram_out;
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wire [31:0] sys_addr;
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// Registers used to mirror internal registers
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// Registers used to mirror internal registers
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reg [15:0] data_xgmctl;
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reg [15:0] data_xgmctl;
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reg [15:0] data_xgchid;
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reg [15:0] data_xgchid;
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reg [15:0] data_xgvbr;
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reg [15:0] data_xgvbr;
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reg [15:0] data_xgswt;
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reg [15:0] data_xgswt;
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reg [15:0] data_xgsem;
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reg [15:0] data_xgsem;
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wire sys_cyc;
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wire sys_stb;
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wire sys_we;
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wire [ 1:0] sys_sel;
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wire [31:0] sys_adr;
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wire [15:0] sys_dout;
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wire host_ack;
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wire [15:0] host_dout;
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wire host_cyc;
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wire host_stb;
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wire host_we;
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wire [ 1:0] host_sel;
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wire [31:0] host_adr;
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wire [15:0] host_din;
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wire xgate_ack;
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wire [15:0] xgate_dout;
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wire xgate_cyc;
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wire xgate_stb;
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wire xgate_we;
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wire [ 1:0] xgate_sel;
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wire [15:0] xgate_adr;
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wire [15:0] xgate_din;
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wire xgate_s_stb;
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wire xgate_s_ack;
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wire [15:0] xgate_s_dout;
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wire slv2_stb;
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wire ram_ack;
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wire [15:0] ram_dout;
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// initial values and testbench setup
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// initial values and testbench setup
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initial
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initial
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begin
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begin
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mstr_test_clk = 0;
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mstr_test_clk = 0;
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vector = 0;
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vector = 0;
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| Line 207... |
Line 238... |
wrap_up;
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wrap_up;
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end
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end
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end
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end
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// Add up errors tha come from WISHBONE read compares
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// Add up errors tha come from WISHBONE read compares
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always @u0.cmp_error_detect
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always @host.cmp_error_detect
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begin
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begin
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error_count <= error_count + 1;
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error_count <= error_count + 1;
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end
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end
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| Line 222... |
Line 253... |
wbm_ack_i <= 1'b0;
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wbm_ack_i <= 1'b0;
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else
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else
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wbm_ack_i <= 1'b1;
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wbm_ack_i <= 1'b1;
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// Write memory interface to RAM
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always @(posedge mstr_test_clk)
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begin
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if (write_mem_strb_l && !write_mem_strb_h && wbm_ack_i)
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ram_8[wbm_adr_o] <= wbm_dat_o[7:0];
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if (write_mem_strb_h && !write_mem_strb_l && wbm_ack_i)
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ram_8[wbm_adr_o] <= wbm_dat_o[7:0];
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if (write_mem_strb_h && write_mem_strb_l && wbm_ack_i)
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begin
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ram_8[wbm_adr_o] <= wbm_dat_o[15:8];
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ram_8[wbm_adr_o+1] <= wbm_dat_o[7:0];
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end
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end
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// Special Memory Mapped Testbench Registers
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// Special Memory Mapped Testbench Registers
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always @(posedge mstr_test_clk or negedge rstn)
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always @(posedge mstr_test_clk or negedge rstn)
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begin
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begin
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if (!rstn)
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if (!rstn)
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begin
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begin
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check_point_reg <= 0;
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check_point_reg <= 0;
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channel_ack_reg <= 0;
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channel_ack_reg <= 0;
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channel_err_reg <= 0;
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channel_err_reg <= 0;
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end
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end
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if (write_mem_strb_l && wbm_ack_i && (wbm_adr_o == CHECK_POINT))
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if (wbm_sel_o[0] && wbm_ack_i && (wbm_adr_o == CHECK_POINT))
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begin
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begin
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check_point_reg <= wbm_dat_o[7:0];
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check_point_reg <= wbm_dat_o[7:0];
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#1;
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#1;
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-> check_point_wrt;
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-> check_point_wrt;
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end
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end
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if (write_mem_strb_l && wbm_ack_i && (wbm_adr_o == CHANNEL_ACK))
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if (wbm_sel_o[0] && wbm_ack_i && (wbm_adr_o == CHANNEL_ACK))
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begin
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begin
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channel_ack_reg <= wbm_dat_o[7:0];
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channel_ack_reg <= wbm_dat_o[7:0];
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#1;
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#1;
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-> channel_ack_wrt;
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-> channel_ack_wrt;
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end
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end
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if (write_mem_strb_l && wbm_ack_i && (wbm_adr_o == CHANNEL_ERR))
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if (wbm_sel_o[0] && wbm_ack_i && (wbm_adr_o == CHANNEL_ERR))
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begin
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begin
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channel_err_reg <= wbm_dat_o[7:0];
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channel_err_reg <= wbm_dat_o[7:0];
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#1;
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#1;
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-> channel_err_wrt;
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-> channel_err_wrt;
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end
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end
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| Line 281... |
Line 298... |
wire [ 6:0] current_active_channel = xgate.risc.xgchid;
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wire [ 6:0] current_active_channel = xgate.risc.xgchid;
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always @channel_ack_wrt
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always @channel_ack_wrt
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clear_channel(current_active_channel);
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clear_channel(current_active_channel);
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// hookup wishbone master model
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wb_master_model #(.dwidth(16), .awidth(32))
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u0 (
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// Outputs
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.cyc(cyc),
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.stb(stb),
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.we(we),
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.sel(),
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.adr(adr),
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.dout(dat_o),
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// inputs
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.din(dat_i),
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.clk(mstr_test_clk),
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.ack(ack),
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.rst(rstn),
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.err(1'b0),
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.rty(1'b0)
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);
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// Address decoding for different XGATE module instances
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// Address decoding for different XGATE module instances
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wire stb0 = stb && ~adr[6] && ~adr[5];
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wire stb0 = host_stb && ~host_adr[6] && ~host_adr[5] && ~|host_adr[31:16];
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wire stb1 = stb && ~adr[6] && adr[5];
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wire stb1 = host_stb && ~host_adr[6] && host_adr[5] && ~|host_adr[31:16];
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wire stb2 = stb && adr[6] && ~adr[5];
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wire stb2 = host_stb && host_adr[6] && ~host_adr[5] && ~|host_adr[31:16];
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wire stb3 = stb && adr[6] && adr[5];
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wire stb3 = host_stb && host_adr[6] && host_adr[5] && ~|host_adr[31:16];
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assign dat1_i = 16'h0000;
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assign dat1_i = 16'h0000;
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assign dat2_i = 16'h0000;
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assign dat2_i = 16'h0000;
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assign dat3_i = 16'h0000;
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assign dat3_i = 16'h0000;
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assign ack_2 = 1'b0;
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assign ack_2 = 1'b0;
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assign ack_3 = 1'b0;
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assign ack_3 = 1'b0;
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assign ack_4 = 1'b0;
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assign ack_4 = 1'b0;
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// Create the Read Data Bus
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// Create the Read Data Bus
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assign dat_i = ({16{stb0}} & dat0_i) |
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assign dat_i = ({16{stb0}} & xgate_s_dout) |
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({16{stb1}} & dat1_i) |
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({16{stb1}} & dat1_i) |
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({16{stb2}} & dat2_i) |
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({16{stb2}} & dat2_i) |
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({16{stb3}} & {8'b0, dat3_i[7:0]});
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({16{stb3}} & {8'b0, dat3_i[7:0]});
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assign ack = ack_1 || ack_2 || ack_3 || ack_4;
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assign ack = xgate_s_ack || ack_2 || ack_3 || ack_4;
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assign wbm_dat_i = {ram_8[wbm_adr_o], ram_8[wbm_adr_o+1]};
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// Aribartration Logic for Testbench RAM access
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assign sys_addr = 1'b1 ? {16'b0, wbm_adr_o} : host_adr;
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// Testbench RAM for Xgate program storage and Load/Store instruction tests
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ram p_ram
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(
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// Outputs
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.ram_out( ram_dout ),
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// inputs
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.address( sys_addr[15:0] ), // sys_addr sys_adr
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.ram_in( sys_dout ),
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.we( sys_we ),
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.ce( 1'b1 ),
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.stb( mstr_test_clk ),
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.sel( sys_sel ) // wbm_sel_o sys_sel
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);
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// hookup wishbone master model
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wb_master_model #(.dwidth(16), .awidth(32))
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host(
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// Outputs
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.cyc( host_cyc ),
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.stb( host_stb ),
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.we( host_we ),
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.sel( host_sel ),
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.adr( host_adr ),
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.dout( host_dout ),
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// inputs
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.din(host_din),
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.clk(mstr_test_clk),
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.ack(host_ack),
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.rst(rstn),
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.err(1'b0),
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.rty(1'b0)
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);
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bus_arbitration #(.dwidth(16),
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.awidth(32))
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arb(
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// System bus I/O
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.sys_cyc( sys_cyc ),
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.sys_stb( sys_stb ),
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.sys_we( sys_we ),
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.sys_sel( sys_sel ),
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.sys_adr( sys_adr ),
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.sys_dout( sys_dout ),
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// Host bus I/O
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.host_ack( host_ack ),
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.host_dout( host_din ),
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.host_cyc( host_cyc ),
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.host_stb( host_stb ),
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.host_we( host_we ),
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.host_sel( host_sel ),
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.host_adr( host_adr ),
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.host_din( host_dout ),
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// Alternate Bus Master #1 Bus I/O
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.alt1_ack( xgate_ack ),
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.alt1_dout( xgate_din ),
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.alt1_cyc( wbm_cyc_o ),
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.alt1_stb( wbm_stb_o ),
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.alt1_we( wbm_we_o ),
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.alt1_sel( wbm_sel_o ),
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.alt1_adr( {16'h0001, wbm_adr_o} ),
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.alt1_din( wbm_dat_o ),
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// Slave #1 Bus I/O
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.slv1_stb( xgate_s_stb ),
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.slv1_ack( xgate_s_ack ),
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.slv1_din( xgate_s_dout ),
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// Slave #2 Bus I/O
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.slv2_stb( slv2_stb ),
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.slv2_ack( wbm_ack_i ),
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.slv2_din( ram_dout ),
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// Miscellaneous
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.host_clk( mstr_test_clk ),
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.risc_clk( mstr_test_clk ),
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.rst( rstn ), // No Connect
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.err( 1'b0 ), // No Connect
|
|
.rty( 1'b0 ) // No Connect
|
|
);
|
// hookup XGATE core - Parameters take all default values
|
// hookup XGATE core - Parameters take all default values
|
// Async Reset, 16 bit Bus, 16 bit Granularity
|
// Async Reset, 16 bit Bus, 8 bit Granularity
|
xgate_top #(.SINGLE_CYCLE(1'b1),
|
xgate_top #(.SINGLE_CYCLE(1'b1),
|
.MAX_CHANNEL(MAX_CHANNEL)) // Max XGATE Interrupt Channel Number
|
.MAX_CHANNEL(MAX_CHANNEL)) // Max XGATE Interrupt Channel Number
|
xgate(
|
xgate(
|
// Wishbone slave interface
|
// Wishbone slave interface
|
.wbs_clk_i( mstr_test_clk ),
|
.wbs_clk_i( mstr_test_clk ),
|
.wbs_rst_i( 1'b0 ), // sync_reset
|
.wbs_rst_i( 1'b0 ), // sync_reset
|
.arst_i( rstn ), // async resetn
|
.arst_i( rstn ), // async resetn
|
.wbs_adr_i( adr[4:0] ),
|
.wbs_adr_i( sys_adr[4:0] ),
|
.wbs_dat_i( dat_o ),
|
.wbs_dat_i( sys_dout ),
|
.wbs_dat_o( dat0_i ),
|
.wbs_dat_o( xgate_s_dout ),
|
.wbs_we_i( we ),
|
.wbs_we_i( sys_we ),
|
.wbs_stb_i( stb0 ),
|
.wbs_stb_i( xgate_s_stb ),
|
.wbs_cyc_i( cyc ),
|
.wbs_cyc_i( sys_cyc ),
|
.wbs_sel_i( 2'b11 ),
|
.wbs_sel_i( sys_sel ),
|
.wbs_ack_o( ack_1 ),
|
.wbs_ack_o( xgate_s_ack ),
|
|
|
// Wishbone master Signals
|
// Wishbone master Signals
|
.wbm_dat_o( wbm_dat_o ),
|
.wbm_dat_o( wbm_dat_o ),
|
.wbm_we_o( wbm_we_o ),
|
.wbm_we_o( wbm_we_o ),
|
.wbm_stb_o( wbm_stb_o ),
|
.wbm_stb_o( wbm_stb_o ),
|
.wbm_cyc_o( wbm_cyc_o ),
|
.wbm_cyc_o( wbm_cyc_o ),
|
.wbm_sel_o( wbm_sel_o ),
|
.wbm_sel_o( wbm_sel_o ),
|
.wbm_adr_o( wbm_adr_o ),
|
.wbm_adr_o( wbm_adr_o ),
|
.wbm_dat_i( wbm_dat_i ),
|
.wbm_dat_i( ram_dout ),
|
.wbm_ack_i( wbm_ack_i ),
|
.wbm_ack_i( wbm_ack_i ),
|
|
|
.xgif( xgif ), // XGATE Interrupt Flag output
|
.xgif( xgif ), // XGATE Interrupt Flag output
|
.xg_sw_irq( xg_sw_irq ), // XGATE Software Error Interrupt Flag output
|
.xg_sw_irq( xg_sw_irq ), // XGATE Software Error Interrupt Flag output
|
.xgswt( xgswt ),
|
.xgswt( xgswt ),
|
.risc_clk( mstr_test_clk ),
|
.risc_clk( mstr_test_clk ),
|
.chan_req_i( {channel_req[MAX_CHANNEL:40], xgswt, channel_req[31:0]} ),
|
.chan_req_i( {channel_req[MAX_CHANNEL:40], xgswt, channel_req[31:0]} ),
|
.write_mem_strb_l( write_mem_strb_l ),
|
|
.write_mem_strb_h( write_mem_strb_h ),
|
|
.scantestmode( scantestmode )
|
.scantestmode( scantestmode )
|
);
|
);
|
|
|
|
|
|
|
| Line 398... |
Line 471... |
|
|
test_debug_bit;
|
test_debug_bit;
|
|
|
test_chid_debug;
|
test_chid_debug;
|
|
|
|
// host_ram;
|
|
// End testing
|
wrap_up;
|
wrap_up;
|
//
|
|
// program core
|
|
//
|
|
|
|
reg_test_16;
|
reg_test_16;
|
|
|
repeat(10) @(posedge mstr_test_clk);
|
repeat(10) @(posedge mstr_test_clk);
|
|
|
wrap_up;
|
wrap_up;
|
end
|
end
|
|
|
|
////////////////////////////////////////////////////////////////////////////////
|
// Test CHID Debug mode operation
|
// Test CHID Debug mode operation
|
task test_chid_debug;
|
task test_chid_debug;
|
begin
|
begin
|
test_num = test_num + 1;
|
test_num = test_num + 1;
|
$display("\nTEST #%d Starts at vector=%d, test_chid_debug", test_num, vector);
|
$display("\nTEST #%d Starts at vector=%d, test_chid_debug", test_num, vector);
|
$readmemh("../../../bench/verilog/debug_test.v", ram_8);
|
$readmemh("../../../bench/verilog/debug_test.v", p_ram.ram_8);
|
|
|
data_xgmctl = XGMCTL_XGBRKIEM | XGMCTL_XGBRKIE;
|
data_xgmctl = XGMCTL_XGBRKIEM | XGMCTL_XGBRKIE;
|
u0.wb_write(0, XGATE_XGMCTL, data_xgmctl); // Enable interrupt on BRK instruction
|
host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD); // Enable interrupt on BRK instruction
|
|
|
activate_thread_sw(3);
|
activate_thread_sw(3);
|
|
|
wait_debug_set; // Debug Status bit is set by BRK instruction
|
wait_debug_set; // Debug Status bit is set by BRK instruction
|
|
|
u0.wb_cmp(0, XGATE_XGPC, 16'h20c6); // See Program code (BRK).
|
host.wb_cmp(0, XGATE_XGPC, 16'h20c6, WORD); // See Program code (BRK).
|
u0.wb_cmp(0, XGATE_XGR3, 16'h0001); // See Program code.R3 = 1
|
host.wb_cmp(0, XGATE_XGR3, 16'h0001, WORD); // See Program code.R3 = 1
|
u0.wb_cmp(0, XGATE_XGCHID, 16'h0003); // Check for Correct CHID
|
host.wb_cmp(0, XGATE_XGCHID, 16'h0003, WORD); // Check for Correct CHID
|
|
|
channel_req[5] = 1'b1; //
|
channel_req[5] = 1'b1; //
|
repeat(7) @(posedge mstr_test_clk);
|
repeat(7) @(posedge mstr_test_clk);
|
u0.wb_cmp(0, XGATE_XGCHID, 16'h0003); // Check for Correct CHID
|
host.wb_cmp(0, XGATE_XGCHID, 16'h0003, WORD); // Check for Correct CHID
|
|
|
u0.wb_write(0, XGATE_XGCHID, 16'h000f); // Change CHID
|
host.wb_write(0, XGATE_XGCHID, 16'h000f, WORD); // Change CHID
|
u0.wb_cmp(0, XGATE_XGCHID, 16'h000f); // Check for Correct CHID
|
host.wb_cmp(0, XGATE_XGCHID, 16'h000f, WORD); // Check for Correct CHID
|
|
|
u0.wb_write(0, XGATE_XGCHID, 16'h0000); // Change CHID to 00, RISC should go to IDLE state
|
host.wb_write(0, XGATE_XGCHID, 16'h0000, WORD); // Change CHID to 00, RISC should go to IDLE state
|
|
|
repeat(1) @(posedge mstr_test_clk);
|
repeat(1) @(posedge mstr_test_clk);
|
|
|
u0.wb_write(0, XGATE_XGCHID, 16'h0004); // Change CHID
|
host.wb_write(0, XGATE_XGCHID, 16'h0004, WORD); // Change CHID
|
|
|
repeat(8) @(posedge mstr_test_clk);
|
repeat(8) @(posedge mstr_test_clk);
|
|
|
data_xgmctl = XGMCTL_XGDBGM;
|
data_xgmctl = XGMCTL_XGDBGM;
|
u0.wb_write(0, XGATE_XGMCTL, data_xgmctl); // Clear Debug Mode Control Bit
|
host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD); // Clear Debug Mode Control Bit
|
|
|
wait_debug_set; // Debug Status bit is set by BRK instruction
|
wait_debug_set; // Debug Status bit is set by BRK instruction
|
u0.wb_cmp(0, XGATE_XGCHID, 16'h0004); // Check for Correct CHID
|
host.wb_cmp(0, XGATE_XGCHID, 16'h0004, WORD); // Check for Correct CHID
|
u0.wb_write(0, XGATE_XGMCTL, data_xgmctl); // Clear Debug Mode Control Bit (Excape from Break State and run)
|
host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD); // Clear Debug Mode Control Bit (Excape from Break State and run)
|
|
|
wait_debug_set; // Debug Status bit is set by BRK instruction
|
wait_debug_set; // Debug Status bit is set by BRK instruction
|
u0.wb_cmp(0, XGATE_XGCHID, 16'h0005); // Check for Correct CHID
|
host.wb_cmp(0, XGATE_XGCHID, 16'h0005, WORD); // Check for Correct CHID
|
activate_channel(6);
|
activate_channel(6);
|
u0.wb_write(0, XGATE_XGMCTL, data_xgmctl); // Clear Debug Mode Control Bit (Excape from Break State and run)
|
host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD); // Clear Debug Mode Control Bit (Excape from Break State and run)
|
|
|
wait_debug_set; // Debug Status bit is set by BRK instruction
|
wait_debug_set; // Debug Status bit is set by BRK instruction
|
u0.wb_cmp(0, XGATE_XGCHID, 16'h0006); // Check for Correct CHID
|
host.wb_cmp(0, XGATE_XGCHID, 16'h0006, WORD); // Check for Correct CHID
|
u0.wb_cmp(0, XGATE_XGPC, 16'h211c); // See Program code (BRK)
|
host.wb_cmp(0, XGATE_XGPC, 16'h211c, WORD); // See Program code (BRK)
|
data_xgmctl = XGMCTL_XGSSM | XGMCTL_XGSS;
|
data_xgmctl = XGMCTL_XGSSM | XGMCTL_XGSS;
|
u0.wb_write(0, XGATE_XGMCTL, data_xgmctl); // Do a Single Step
|
host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD); // Do a Single Step
|
repeat(8) @(posedge mstr_test_clk);
|
repeat(8) @(posedge mstr_test_clk);
|
u0.wb_cmp(0, XGATE_XGPC, 16'h211e); // See Program code (BRA)
|
host.wb_cmp(0, XGATE_XGPC, 16'h211e, WORD); // See Program code (BRA)
|
u0.wb_write(0, XGATE_XGMCTL, data_xgmctl); // Do a Single Step
|
host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD); // Do a Single Step
|
repeat(8) @(posedge mstr_test_clk);
|
repeat(8) @(posedge mstr_test_clk);
|
u0.wb_cmp(0, XGATE_XGPC, 16'h2122); // See Program code ()
|
host.wb_cmp(0, XGATE_XGPC, 16'h2122, WORD); // See Program code ()
|
|
|
repeat(20) @(posedge mstr_test_clk);
|
repeat(20) @(posedge mstr_test_clk);
|
|
|
data_xgmctl = XGMCTL_XGDBGM;
|
data_xgmctl = XGMCTL_XGDBGM;
|
u0.wb_write(0, XGATE_XGMCTL, data_xgmctl); // Clear Debug Mode Control Bit
|
host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD); // Clear Debug Mode Control Bit
|
|
|
repeat(50) @(posedge mstr_test_clk);
|
repeat(50) @(posedge mstr_test_clk);
|
|
|
|
p_ram.dump_ram(0);
|
|
|
end
|
end
|
endtask
|
endtask
|
|
|
|
////////////////////////////////////////////////////////////////////////////////
|
// Test Debug bit operation
|
// Test Debug bit operation
|
task test_debug_bit;
|
task test_debug_bit;
|
begin
|
begin
|
test_num = test_num + 1;
|
test_num = test_num + 1;
|
$display("\nTEST #%d Starts at vector=%d, test_debug_bit", test_num, vector);
|
$display("\nTEST #%d Starts at vector=%d, test_debug_bit", test_num, vector);
|
$readmemh("../../../bench/verilog/debug_test.v", ram_8);
|
$readmemh("../../../bench/verilog/debug_test.v", p_ram.ram_8);
|
|
|
data_xgmctl = XGMCTL_XGBRKIEM | XGMCTL_XGBRKIE;
|
data_xgmctl = XGMCTL_XGBRKIEM | XGMCTL_XGBRKIE;
|
u0.wb_write(0, XGATE_XGMCTL, data_xgmctl); // Enable interrupt on BRK instruction
|
host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD); // Enable interrupt on BRK instruction
|
|
|
activate_thread_sw(2);
|
activate_thread_sw(2);
|
|
|
repeat(25) @(posedge mstr_test_clk);
|
repeat(25) @(posedge mstr_test_clk);
|
|
|
data_xgmctl = XGMCTL_XGDBGM | XGMCTL_XGDBG;
|
data_xgmctl = XGMCTL_XGDBGM | XGMCTL_XGDBG;
|
u0.wb_write(0, XGATE_XGMCTL, data_xgmctl); // Set Debug Mode Control Bit
|
host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD); // Set Debug Mode Control Bit
|
repeat(5) @(posedge mstr_test_clk);
|
repeat(5) @(posedge mstr_test_clk);
|
|
|
u0.wb_read(1, XGATE_XGR3, q);
|
host.wb_read(1, XGATE_XGR3, q, WORD);
|
data_xgmctl = XGMCTL_XGSSM | XGMCTL_XGSS;
|
data_xgmctl = XGMCTL_XGSSM | XGMCTL_XGSS;
|
qq = q;
|
qq = q;
|
|
|
// The Xgate test program is in an infinate loop incrementing R3
|
// The Xgate test program is in an infinate loop incrementing R3
|
while (qq == q) // Look for change in R3 register
|
while (qq == q) // Look for change in R3 register
|
begin
|
begin
|
u0.wb_write(0, XGATE_XGMCTL, data_xgmctl); // Do a Single Step
|
host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD); // Do a Single Step
|
repeat(5) @(posedge mstr_test_clk);
|
repeat(5) @(posedge mstr_test_clk);
|
u0.wb_read(1, XGATE_XGR3, q);
|
host.wb_read(1, XGATE_XGR3, q, WORD);
|
end
|
end
|
if (q != (qq+1))
|
if (q != (qq+1))
|
begin
|
begin
|
$display("Error! - Unexpected value of R3 at vector=%d", vector);
|
$display("Error! - Unexpected value of R3 at vector=%d", vector);
|
error_count = error_count + 1;
|
error_count = error_count + 1;
|
end
|
end
|
|
|
|
|
u0.wb_write(1, XGATE_XGPC, 16'h2094); // Write to PC to force exit from infinate loop
|
host.wb_write(1, XGATE_XGPC, 16'h2094, WORD); // Write to PC to force exit from infinate loop
|
repeat(5) @(posedge mstr_test_clk);
|
repeat(5) @(posedge mstr_test_clk);
|
|
|
data_xgmctl = XGMCTL_XGSSM | XGMCTL_XGSS;
|
data_xgmctl = XGMCTL_XGSSM | XGMCTL_XGSS;
|
u0.wb_write(0, XGATE_XGMCTL, data_xgmctl); // Do a Single Step (Load ADDL instruction)
|
host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD); // Do a Single Step (Load ADDL instruction)
|
repeat(5) @(posedge mstr_test_clk);
|
repeat(5) @(posedge mstr_test_clk);
|
u0.wb_cmp(0, XGATE_XGR4, 16'h0002); // See Program code.(R4 <= R4 + 1)
|
host.wb_cmp(0, XGATE_XGR4, 16'h0002, WORD); // See Program code.(R4 <= R4 + 1)
|
|
|
u0.wb_write(0, XGATE_XGMCTL, data_xgmctl); // Do a Single Step (Load ADDL instruction)
|
host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD); // Do a Single Step (Load ADDL instruction)
|
repeat(5) @(posedge mstr_test_clk);
|
repeat(5) @(posedge mstr_test_clk);
|
u0.wb_cmp(0, XGATE_XGR4, 16'h0003); // See Program code.(R4 <= R4 + 1)
|
host.wb_cmp(0, XGATE_XGR4, 16'h0003, WORD); // See Program code.(R4 <= R4 + 1)
|
|
|
data_xgmctl = XGMCTL_XGDBGM;
|
data_xgmctl = XGMCTL_XGDBGM;
|
u0.wb_write(0, XGATE_XGMCTL, data_xgmctl); // Clear Debug Mode Control Bit
|
host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD); // Clear Debug Mode Control Bit
|
// Should be back in Run Mode
|
// Should be back in Run Mode
|
|
|
// data_xgmctl = XGMCTL_XGSWEIFM | XGMCTL_XGSWEIF | XGMCTL_XGBRKIEM;
|
// data_xgmctl = XGMCTL_XGSWEIFM | XGMCTL_XGSWEIF | XGMCTL_XGBRKIEM;
|
// u0.wb_write(0, XGATE_XGMCTL, data_xgmctl); // Clear Software Interrupt and BRK Interrupt Enable Bit
|
// host.wb_write(0, XGATE_XGMCTL, data_xgmctl); // Clear Software Interrupt and BRK Interrupt Enable Bit
|
repeat(15) @(posedge mstr_test_clk);
|
repeat(15) @(posedge mstr_test_clk);
|
|
|
end
|
end
|
endtask
|
endtask
|
|
|
|
////////////////////////////////////////////////////////////////////////////////
|
// Test Debug mode operation
|
// Test Debug mode operation
|
task test_debug_mode;
|
task test_debug_mode;
|
begin
|
begin
|
test_num = test_num + 1;
|
test_num = test_num + 1;
|
$display("\nTEST #%d Starts at vector=%d, test_debug_mode", test_num, vector);
|
$display("\nTEST #%d Starts at vector=%d, test_debug_mode", test_num, vector);
|
$readmemh("../../../bench/verilog/debug_test.v", ram_8);
|
$readmemh("../../../bench/verilog/debug_test.v", p_ram.ram_8);
|
|
|
data_xgmctl = XGMCTL_XGBRKIEM | XGMCTL_XGBRKIE;
|
data_xgmctl = XGMCTL_XGBRKIEM | XGMCTL_XGBRKIE;
|
u0.wb_write(0, XGATE_XGMCTL, data_xgmctl); // Enable interrupt on BRK instruction
|
host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD); // Enable interrupt on BRK instruction
|
|
|
activate_thread_sw(1);
|
activate_thread_sw(1);
|
|
|
wait_debug_set; // Debug Status bit is set by BRK instruction
|
wait_debug_set; // Debug Status bit is set by BRK instruction
|
|
|
u0.wb_cmp(0, XGATE_XGPC, 16'h203a); // See Program code (BRK).
|
host.wb_cmp(0, XGATE_XGPC, 16'h203a, WORD); // See Program code (BRK).
|
u0.wb_cmp(0, XGATE_XGR3, 16'h0001); // See Program code.R3 = 1
|
host.wb_cmp(0, XGATE_XGR3, 16'h0001, WORD); // See Program code.R3 = 1
|
|
|
data_xgmctl = XGMCTL_XGSSM | XGMCTL_XGSS;
|
data_xgmctl = XGMCTL_XGSSM | XGMCTL_XGSS;
|
|
|
u0.wb_write(0, XGATE_XGMCTL, data_xgmctl); // Do a Single Step (Load ADDL instruction)
|
host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD); // Do a Single Step (Load ADDL instruction)
|
repeat(5) @(posedge mstr_test_clk);
|
repeat(5) @(posedge mstr_test_clk);
|
u0.wb_cmp(0, XGATE_XGPC, 16'h203c); // PC + 2.
|
host.wb_cmp(0, XGATE_XGPC, 16'h203c, WORD); // PC + 2.
|
|
|
u0.wb_write(0, XGATE_XGMCTL, data_xgmctl); // Do a Single Step (Load NOP instruction)
|
host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD); // Do a Single Step (Load NOP instruction)
|
repeat(5) @(posedge mstr_test_clk); // Execute ADDL instruction
|
repeat(5) @(posedge mstr_test_clk); // Execute ADDL instruction
|
u0.wb_cmp(0, XGATE_XGR3, 16'h0002); // See Program code.(R3 <= R3 + 1)
|
host.wb_cmp(0, XGATE_XGR3, 16'h0002, WORD); // See Program code.(R3 <= R3 + 1)
|
u0.wb_cmp(0, XGATE_XGCCR, 16'h0000); // See Program code.
|
host.wb_cmp(0, XGATE_XGCCR, 16'h0000, WORD); // See Program code.
|
u0.wb_cmp(0, XGATE_XGPC, 16'h203e); // PC + 2.
|
host.wb_cmp(0, XGATE_XGPC, 16'h203e, WORD); // PC + 2.
|
repeat(5) @(posedge mstr_test_clk);
|
repeat(5) @(posedge mstr_test_clk);
|
u0.wb_cmp(0, XGATE_XGPC, 16'h203e); // Still no change.
|
host.wb_cmp(0, XGATE_XGPC, 16'h203e, WORD); // Still no change.
|
|
|
u0.wb_write(0, XGATE_XGMCTL, data_xgmctl); // Do a Single Step (Load BRA instruction)
|
host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD); // Do a Single Step (Load BRA instruction)
|
repeat(9) @(posedge mstr_test_clk); // Execute NOP instruction
|
repeat(9) @(posedge mstr_test_clk); // Execute NOP instruction
|
u0.wb_cmp(0, XGATE_XGPC, 16'h2040); // See Program code.
|
host.wb_cmp(0, XGATE_XGPC, 16'h2040, WORD); // See Program code.
|
|
|
|
|
u0.wb_write(0, XGATE_XGMCTL, data_xgmctl); // Do a Single Step
|
host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD); // Do a Single Step
|
repeat(5) @(posedge mstr_test_clk); // Execute BRA instruction
|
repeat(5) @(posedge mstr_test_clk); // Execute BRA instruction
|
u0.wb_cmp(0, XGATE_XGPC, 16'h2064); // PC = Branch destination.
|
host.wb_cmp(0, XGATE_XGPC, 16'h2064, WORD); // PC = Branch destination.
|
// Load ADDL instruction
|
// Load ADDL instruction
|
|
|
u0.wb_write(0, XGATE_XGMCTL, data_xgmctl); // Do a Single Step (Load LDW R7 instruction)
|
host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD); // Do a Single Step (Load LDW R7 instruction)
|
repeat(5) @(posedge mstr_test_clk); // Execute ADDL instruction
|
repeat(5) @(posedge mstr_test_clk); // Execute ADDL instruction
|
u0.wb_cmp(0, XGATE_XGPC, 16'h2066); // PC + 2.
|
host.wb_cmp(0, XGATE_XGPC, 16'h2066, WORD); // PC + 2.
|
u0.wb_cmp(0, XGATE_XGR3, 16'h0003); // See Program code.(R3 <= R3 + 1)
|
host.wb_cmp(0, XGATE_XGR3, 16'h0003, WORD); // See Program code.(R3 <= R3 + 1)
|
|
|
u0.wb_write(0, XGATE_XGMCTL, data_xgmctl); // Do a Single Step (LDW R7)
|
host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD); // Do a Single Step (LDW R7)
|
repeat(5) @(posedge mstr_test_clk);
|
repeat(5) @(posedge mstr_test_clk);
|
u0.wb_cmp(0, XGATE_XGPC, 16'h2068); // PC + 2.
|
host.wb_cmp(0, XGATE_XGPC, 16'h2068, WORD); // PC + 2.
|
u0.wb_cmp(0, XGATE_XGR7, 16'h00c3); // See Program code
|
host.wb_cmp(0, XGATE_XGR7, 16'h00c3, WORD); // See Program code
|
|
|
repeat(1) @(posedge mstr_test_clk);
|
repeat(1) @(posedge mstr_test_clk);
|
u0.wb_write(0, XGATE_XGMCTL, data_xgmctl); // Do a Single Step (BRA)
|
host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD); // Do a Single Step (BRA)
|
repeat(9) @(posedge mstr_test_clk);
|
repeat(9) @(posedge mstr_test_clk);
|
u0.wb_cmp(0, XGATE_XGPC, 16'h2048); // See Program code.
|
host.wb_cmp(0, XGATE_XGPC, 16'h2048, WORD); // See Program code.
|
|
|
u0.wb_write(0, XGATE_XGMCTL, data_xgmctl); // Do a Single Step (STW R3)
|
host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD); // Do a Single Step (STW R3)
|
repeat(5) @(posedge mstr_test_clk);
|
repeat(5) @(posedge mstr_test_clk);
|
u0.wb_cmp(0, XGATE_XGPC, 16'h204a); // PC + 2.
|
host.wb_cmp(0, XGATE_XGPC, 16'h204a, WORD); // PC + 2.
|
u0.wb_cmp(0, XGATE_XGR3, 16'h0003); // See Program code.(R3 <= R3 + 1)
|
host.wb_cmp(0, XGATE_XGR3, 16'h0003, WORD); // See Program code.(R3 <= R3 + 1)
|
|
|
u0.wb_write(0, XGATE_XGMCTL, data_xgmctl); // Do a Single Step (R3 <= R3 + 1)
|
host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD); // Do a Single Step (R3 <= R3 + 1)
|
repeat(5) @(posedge mstr_test_clk);
|
repeat(5) @(posedge mstr_test_clk);
|
u0.wb_cmp(0, XGATE_XGPC, 16'h204c); // PC + 2.
|
host.wb_cmp(0, XGATE_XGPC, 16'h204c, WORD); // PC + 2.
|
|
|
repeat(5) @(posedge mstr_test_clk);
|
repeat(5) @(posedge mstr_test_clk);
|
|
|
data_xgmctl = XGMCTL_XGDBGM;
|
data_xgmctl = XGMCTL_XGDBGM;
|
u0.wb_write(0, XGATE_XGMCTL, data_xgmctl); // Clear Debug Mode Control Bit
|
host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD); // Clear Debug Mode Control Bit
|
// Should be back in Run Mode
|
// Should be back in Run Mode
|
wait_irq_set(1);
|
wait_irq_set(1);
|
u0.wb_write(1, XGATE_XGIF_0, 16'h0002);
|
host.wb_write(1, XGATE_XGIF_0, 16'h0002, WORD);
|
|
|
data_xgmctl = XGMCTL_XGSWEIFM | XGMCTL_XGSWEIF | XGMCTL_XGBRKIEM;
|
data_xgmctl = XGMCTL_XGSWEIFM | XGMCTL_XGSWEIF | XGMCTL_XGBRKIEM;
|
u0.wb_write(0, XGATE_XGMCTL, data_xgmctl); // Clear Software Interrupt and BRK Interrupt Enable Bit
|
host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD); // Clear Software Interrupt and BRK Interrupt Enable Bit
|
repeat(15) @(posedge mstr_test_clk);
|
repeat(15) @(posedge mstr_test_clk);
|
|
|
end
|
end
|
endtask
|
endtask
|
|
|
|
////////////////////////////////////////////////////////////////////////////////
|
// Test instruction set
|
// Test instruction set
|
task test_inst_set;
|
task test_inst_set;
|
begin
|
begin
|
$readmemh("../../../bench/verilog/inst_test.v", ram_8);
|
$readmemh("../../../bench/verilog/inst_test.v", p_ram.ram_8);
|
test_num = test_num + 1;
|
test_num = test_num + 1;
|
$display("\nTEST #%d Starts at vector=%d, inst_test", test_num, vector);
|
$display("\nTEST #%d Starts at vector=%d, inst_test", test_num, vector);
|
repeat(1) @(posedge mstr_test_clk);
|
repeat(1) @(posedge mstr_test_clk);
|
|
|
activate_thread_sw(1);
|
activate_thread_sw(1);
|
wait_irq_set(1);
|
wait_irq_set(1);
|
u0.wb_write(1, XGATE_XGIF_0, 16'h0002);
|
host.wb_write(1, XGATE_XGIF_0, 16'h0002, WORD);
|
|
|
activate_thread_sw(2);
|
activate_thread_sw(2);
|
wait_irq_set(2);
|
wait_irq_set(2);
|
u0.wb_write(1, XGATE_XGIF_0, 16'h0004);
|
host.wb_write(1, XGATE_XGIF_0, 16'h0004, WORD);
|
|
|
activate_thread_sw(3);
|
activate_thread_sw(3);
|
wait_irq_set(3);
|
wait_irq_set(3);
|
u0.wb_write(1, XGATE_XGIF_0, 16'h0008);
|
host.wb_write(1, XGATE_XGIF_0, 16'h0008, WORD);
|
|
|
activate_thread_sw(4);
|
activate_thread_sw(4);
|
wait_irq_set(4);
|
wait_irq_set(4);
|
u0.wb_write(1, XGATE_XGIF_0, 16'h0010);
|
host.wb_write(1, XGATE_XGIF_0, 16'h0010, WORD);
|
|
|
activate_thread_sw(5);
|
activate_thread_sw(5);
|
wait_irq_set(5);
|
wait_irq_set(5);
|
u0.wb_write(1, XGATE_XGIF_0, 16'h0020);
|
host.wb_write(1, XGATE_XGIF_0, 16'h0020, WORD);
|
|
|
activate_thread_sw(6);
|
activate_thread_sw(6);
|
wait_irq_set(6);
|
wait_irq_set(6);
|
u0.wb_write(1, XGATE_XGIF_0, 16'h0040);
|
host.wb_write(1, XGATE_XGIF_0, 16'h0040, WORD);
|
|
|
activate_thread_sw(7);
|
activate_thread_sw(7);
|
wait_irq_set(7);
|
wait_irq_set(7);
|
u0.wb_write(1, XGATE_XGIF_0, 16'h0080);
|
host.wb_write(1, XGATE_XGIF_0, 16'h0080, WORD);
|
|
|
activate_thread_sw(8);
|
activate_thread_sw(8);
|
wait_irq_set(8);
|
wait_irq_set(8);
|
u0.wb_write(1, XGATE_XGIF_0, 16'h0100);
|
host.wb_write(1, XGATE_XGIF_0, 16'h0100, WORD);
|
|
|
activate_thread_sw(9);
|
activate_thread_sw(9);
|
wait_irq_set(9);
|
wait_irq_set(9);
|
u0.wb_write(1, XGATE_XGIF_0, 16'h0200);
|
host.wb_write(1, XGATE_XGIF_0, 16'h0200, WORD);
|
|
|
u0.wb_write(1, XGATE_XGSEM, 16'h5050);
|
host.wb_write(1, XGATE_XGSEM, 16'h5050, WORD);
|
u0.wb_cmp(0, XGATE_XGSEM, 16'h0050); //
|
host.wb_cmp(0, XGATE_XGSEM, 16'h0050, WORD); //
|
activate_thread_sw(10);
|
activate_thread_sw(10);
|
wait_irq_set(10);
|
wait_irq_set(10);
|
u0.wb_write(1, XGATE_XGIF_0, 16'h0400);
|
host.wb_write(1, XGATE_XGIF_0, 16'h0400, WORD);
|
|
|
u0.wb_write(1, XGATE_XGSEM, 16'hff00); // clear the old settings
|
host.wb_write(1, XGATE_XGSEM, 16'hff00, WORD); // clear the old settings
|
u0.wb_cmp(0, XGATE_XGSEM, 16'h0000); //
|
host.wb_cmp(0, XGATE_XGSEM, 16'h0000, WORD); //
|
u0.wb_write(1, XGATE_XGSEM, 16'ha0a0); // Verify that bits were unlocked by RISC
|
host.wb_write(1, XGATE_XGSEM, 16'ha0a0, WORD); // Verify that bits were unlocked by RISC
|
u0.wb_cmp(0, XGATE_XGSEM, 16'h00a0); // Verify bits were set
|
host.wb_cmp(0, XGATE_XGSEM, 16'h00a0, WORD); // Verify bits were set
|
u0.wb_write(1, XGATE_XGSEM, 16'hff08); // Try to set the bit that was left locked by the RISC
|
host.wb_write(1, XGATE_XGSEM, 16'hff08, WORD); // Try to set the bit that was left locked by the RISC
|
u0.wb_cmp(0, XGATE_XGSEM, 16'h0000); // Verify no bits were set
|
host.wb_cmp(0, XGATE_XGSEM, 16'h0000, WORD); // Verify no bits were set
|
|
|
repeat(20) @(posedge mstr_test_clk);
|
repeat(20) @(posedge mstr_test_clk);
|
|
|
dump_ram(0);
|
p_ram.dump_ram(0);
|
|
|
end
|
end
|
endtask
|
endtask
|
|
|
|
////////////////////////////////////////////////////////////////////////////////
|
// check register bits - reset, read/write
|
// check register bits - reset, read/write
|
task reg_test_16;
|
task reg_test_16;
|
begin
|
begin
|
test_num = test_num + 1;
|
test_num = test_num + 1;
|
$display("TEST #%d Starts at vector=%d, reg_test_16", test_num, vector);
|
$display("TEST #%d Starts at vector=%d, reg_test_16", test_num, vector);
|
u0.wb_cmp(0, XGATE_XGMCTL, 16'h0000); // verify reset
|
host.wb_cmp(0, XGATE_XGMCTL, 16'h0000, WORD); // verify reset
|
u0.wb_cmp(0, XGATE_XGCHID, 16'h0000); // verify reset
|
host.wb_cmp(0, XGATE_XGCHID, 16'h0000, WORD); // verify reset
|
u0.wb_cmp(0, XGATE_XGISPHI, 16'h0000); // verify reset
|
host.wb_cmp(0, XGATE_XGISPHI, 16'h0000, WORD); // verify reset
|
u0.wb_cmp(0, XGATE_XGISPLO, 16'h0000); // verify reset
|
host.wb_cmp(0, XGATE_XGISPLO, 16'h0000, WORD); // verify reset
|
u0.wb_cmp(0, XGATE_XGVBR, 16'h0000); // verify reset
|
host.wb_cmp(0, XGATE_XGVBR, 16'h0000, WORD); // verify reset
|
u0.wb_cmp(0, XGATE_XGIF_7, 16'h0000); // verify reset
|
host.wb_cmp(0, XGATE_XGIF_7, 16'h0000, WORD); // verify reset
|
u0.wb_cmp(0, XGATE_XGIF_6, 16'h0000); // verify reset
|
host.wb_cmp(0, XGATE_XGIF_6, 16'h0000, WORD); // verify reset
|
u0.wb_cmp(0, XGATE_XGIF_5, 16'h0000); // verify reset
|
host.wb_cmp(0, XGATE_XGIF_5, 16'h0000, WORD); // verify reset
|
u0.wb_cmp(0, XGATE_XGIF_4, 16'h0000); // verify reset
|
host.wb_cmp(0, XGATE_XGIF_4, 16'h0000, WORD); // verify reset
|
u0.wb_cmp(0, XGATE_XGIF_3, 16'h0000); // verify reset
|
host.wb_cmp(0, XGATE_XGIF_3, 16'h0000, WORD); // verify reset
|
u0.wb_cmp(0, XGATE_XGIF_2, 16'h0000); // verify reset
|
host.wb_cmp(0, XGATE_XGIF_2, 16'h0000, WORD); // verify reset
|
u0.wb_cmp(0, XGATE_XGIF_1, 16'h0000); // verify reset
|
host.wb_cmp(0, XGATE_XGIF_1, 16'h0000, WORD); // verify reset
|
u0.wb_cmp(0, XGATE_XGIF_0, 16'h0000); // verify reset
|
host.wb_cmp(0, XGATE_XGIF_0, 16'h0000, WORD); // verify reset
|
u0.wb_cmp(0, XGATE_XGSWT, 16'h0000); // verify reset
|
host.wb_cmp(0, XGATE_XGSWT, 16'h0000, WORD); // verify reset
|
u0.wb_cmp(0, XGATE_XGSEM, 16'h0000); // verify reset
|
host.wb_cmp(0, XGATE_XGSEM, 16'h0000, WORD); // verify reset
|
u0.wb_cmp(0, XGATE_XGCCR, 16'h0000); // verify reset
|
host.wb_cmp(0, XGATE_XGCCR, 16'h0000, WORD); // verify reset
|
u0.wb_cmp(0, XGATE_XGPC, 16'h0000); // verify reset
|
host.wb_cmp(0, XGATE_XGPC, 16'h0000, WORD); // verify reset
|
u0.wb_cmp(0, XGATE_XGR1, 16'h0000); // verify reset
|
host.wb_cmp(0, XGATE_XGR1, 16'h0000, WORD); // verify reset
|
u0.wb_cmp(0, XGATE_XGR2, 16'h0000); // verify reset
|
host.wb_cmp(0, XGATE_XGR2, 16'h0000, WORD); // verify reset
|
u0.wb_cmp(0, XGATE_XGR3, 16'h0000); // verify reset
|
host.wb_cmp(0, XGATE_XGR3, 16'h0000, WORD); // verify reset
|
u0.wb_cmp(0, XGATE_XGR4, 16'h0000); // verify reset
|
host.wb_cmp(0, XGATE_XGR4, 16'h0000, WORD); // verify reset
|
u0.wb_cmp(0, XGATE_XGR5, 16'h0000); // verify reset
|
host.wb_cmp(0, XGATE_XGR5, 16'h0000, WORD); // verify reset
|
u0.wb_cmp(0, XGATE_XGR6, 16'h0000); // verify reset
|
host.wb_cmp(0, XGATE_XGR6, 16'h0000, WORD); // verify reset
|
u0.wb_cmp(0, XGATE_XGR7, 16'h0000); // verify reset
|
host.wb_cmp(0, XGATE_XGR7, 16'h0000, WORD); // verify reset
|
|
|
u0.wb_write(1, XGATE_XGR1, 16'h5555);
|
host.wb_write(1, XGATE_XGR1, 16'h5555, WORD);
|
u0.wb_cmp( 0, XGATE_XGR1, 16'h5555);
|
host.wb_cmp( 0, XGATE_XGR1, 16'h5555, WORD);
|
u0.wb_write(1, XGATE_XGR2, 16'haaaa);
|
host.wb_write(1, XGATE_XGR2, 16'haaaa, WORD);
|
u0.wb_cmp( 0, XGATE_XGR2, 16'haaaa);
|
host.wb_cmp( 0, XGATE_XGR2, 16'haaaa, WORD);
|
u0.wb_write(1, XGATE_XGR3, 16'h9999);
|
host.wb_write(1, XGATE_XGR3, 16'h9999, WORD);
|
u0.wb_cmp( 0, XGATE_XGR3, 16'h9999);
|
host.wb_cmp( 0, XGATE_XGR3, 16'h9999, WORD);
|
u0.wb_write(1, XGATE_XGR4, 16'hcccc);
|
host.wb_write(1, XGATE_XGR4, 16'hcccc, WORD);
|
u0.wb_cmp( 0, XGATE_XGR4, 16'hcccc);
|
host.wb_cmp( 0, XGATE_XGR4, 16'hcccc, WORD);
|
u0.wb_write(1, XGATE_XGR5, 16'h3333);
|
host.wb_write(1, XGATE_XGR5, 16'h3333, WORD);
|
u0.wb_cmp( 0, XGATE_XGR5, 16'h3333);
|
host.wb_cmp( 0, XGATE_XGR5, 16'h3333, WORD);
|
u0.wb_write(1, XGATE_XGR6, 16'h6666);
|
host.wb_write(1, XGATE_XGR6, 16'h6666, WORD);
|
u0.wb_cmp( 0, XGATE_XGR6, 16'h6666);
|
host.wb_cmp( 0, XGATE_XGR6, 16'h6666, WORD);
|
u0.wb_write(1, XGATE_XGR7, 16'ha5a5);
|
host.wb_write(1, XGATE_XGR7, 16'ha5a5, WORD);
|
u0.wb_cmp( 0, XGATE_XGR7, 16'ha5a5);
|
host.wb_cmp( 0, XGATE_XGR7, 16'ha5a5, WORD);
|
|
|
u0.wb_write(1, XGATE_XGPC, 16'h5a5a);
|
host.wb_write(1, XGATE_XGPC, 16'h5a5a, WORD);
|
u0.wb_cmp( 0, XGATE_XGPC, 16'h5a5a);
|
host.wb_cmp( 0, XGATE_XGPC, 16'h5a5a, WORD);
|
|
|
u0.wb_write(1, XGATE_XGCCR, 16'hfffa);
|
host.wb_write(1, XGATE_XGCCR, 16'hfffa, WORD);
|
u0.wb_cmp( 0, XGATE_XGCCR, 16'h000a);
|
host.wb_cmp( 0, XGATE_XGCCR, 16'h000a, WORD);
|
u0.wb_write(1, XGATE_XGCCR, 16'hfff5);
|
host.wb_write(1, XGATE_XGCCR, 16'hfff5, WORD);
|
u0.wb_cmp( 0, XGATE_XGCCR, 16'h0005);
|
host.wb_cmp( 0, XGATE_XGCCR, 16'h0005, WORD);
|
|
|
end
|
end
|
endtask
|
endtask
|
|
|
|
|
|
////////////////////////////////////////////////////////////////////////////////
|
|
// check RAM Read/Write from host
|
|
task host_ram;
|
|
begin
|
|
test_num = test_num + 1;
|
|
$display("TEST #%d Starts at vector=%d, host_ram", test_num, vector);
|
|
|
|
host.wb_write(1, SYS_RAM_BASE, 16'h5555, WORD);
|
|
host.wb_cmp( 0, SYS_RAM_BASE, 16'h5555, WORD);
|
|
|
|
repeat(5) @(posedge mstr_test_clk);
|
|
p_ram.dump_ram(0);
|
|
|
|
end
|
|
endtask
|
|
|
|
////////////////////////////////////////////////////////////////////////////////
|
// Poll for XGATE Interrupt set
|
// Poll for XGATE Interrupt set
|
task wait_irq_set;
|
task wait_irq_set;
|
input [ 6:0] chan_val;
|
input [ 6:0] chan_val;
|
begin
|
begin
|
while(!xgif[chan_val])
|
while(!xgif[chan_val])
|
@(posedge mstr_test_clk); // poll it until it is set
|
@(posedge mstr_test_clk); // poll it until it is set
|
$display("XGATE Interrupt Request #%d set detected at vector =%d", chan_val, vector);
|
$display("XGATE Interrupt Request #%d set detected at vector =%d", chan_val, vector);
|
end
|
end
|
endtask
|
endtask
|
|
|
|
////////////////////////////////////////////////////////////////////////////////
|
// Poll for debug bit set
|
// Poll for debug bit set
|
task wait_debug_set;
|
task wait_debug_set;
|
begin
|
begin
|
u0.wb_read(1, XGATE_XGMCTL, q);
|
host.wb_read(1, XGATE_XGMCTL, q, WORD);
|
while(~|(q & XGMCTL_XGDBG))
|
while(~|(q & XGMCTL_XGDBG))
|
u0.wb_read(1, XGATE_XGMCTL, q); // poll it until it is set
|
host.wb_read(1, XGATE_XGMCTL, q, WORD); // poll it until it is set
|
$display("DEBUG Flag set detected at vector =%d", vector);
|
$display("DEBUG Flag set detected at vector =%d", vector);
|
end
|
end
|
endtask
|
endtask
|
|
|
|
|
|
////////////////////////////////////////////////////////////////////////////////
|
task system_reset; // reset system
|
task system_reset; // reset system
|
begin
|
begin
|
repeat(1) @(posedge mstr_test_clk);
|
repeat(1) @(posedge mstr_test_clk);
|
sync_reset = 1'b1; // Make the sync reset 1 clock cycle long
|
sync_reset = 1'b1; // Make the sync reset 1 clock cycle long
|
#2; // move the async reset away from the clock edge
|
#2; // move the async reset away from the clock edge
|
| Line 775... |
Line 874... |
repeat(2) @(posedge mstr_test_clk);
|
repeat(2) @(posedge mstr_test_clk);
|
end
|
end
|
endtask
|
endtask
|
|
|
|
|
|
////////////////////////////////////////////////////////////////////////////////
|
task activate_channel;
|
task activate_channel;
|
input [ 6:0] chan_val;
|
input [ 6:0] chan_val;
|
begin
|
begin
|
$display("Activating Channel %d", chan_val);
|
$display("Activating Channel %d", chan_val);
|
|
|
| Line 786... |
Line 886... |
repeat(1) @(posedge mstr_test_clk);
|
repeat(1) @(posedge mstr_test_clk);
|
end
|
end
|
endtask
|
endtask
|
|
|
|
|
|
////////////////////////////////////////////////////////////////////////////////
|
task clear_channel;
|
task clear_channel;
|
input [ 6:0] chan_val;
|
input [ 6:0] chan_val;
|
begin
|
begin
|
$display("Clearing Channel interrupt input #%d", chan_val);
|
$display("Clearing Channel interrupt input #%d", chan_val);
|
|
|
| Line 797... |
Line 898... |
repeat(1) @(posedge mstr_test_clk);
|
repeat(1) @(posedge mstr_test_clk);
|
end
|
end
|
endtask
|
endtask
|
|
|
|
|
|
////////////////////////////////////////////////////////////////////////////////
|
task clear_irq_flag;
|
task clear_irq_flag;
|
input [ 6:0] chan_val;
|
input [ 6:0] chan_val;
|
begin
|
begin
|
$display("Clearing Channel interrupt flag #%d", chan_val);
|
$display("Clearing Channel interrupt flag #%d", chan_val);
|
if (0 < chan_val < 16)
|
if (0 < chan_val < 16)
|
u0.wb_write(1, XGATE_XGIF_0, 16'hffff);
|
host.wb_write(1, XGATE_XGIF_0, 16'hffff, WORD);
|
if (15 < chan_val < 32)
|
if (15 < chan_val < 32)
|
u0.wb_write(1, XGATE_XGIF_1, 16'hffff);
|
host.wb_write(1, XGATE_XGIF_1, 16'hffff, WORD);
|
if (31 < chan_val < 48)
|
if (31 < chan_val < 48)
|
u0.wb_write(1, XGATE_XGIF_2, 16'hffff);
|
host.wb_write(1, XGATE_XGIF_2, 16'hffff, WORD);
|
if (47 < chan_val < 64)
|
if (47 < chan_val < 64)
|
u0.wb_write(1, XGATE_XGIF_3, 16'hffff);
|
host.wb_write(1, XGATE_XGIF_3, 16'hffff, WORD);
|
if (63 < chan_val < 80)
|
if (63 < chan_val < 80)
|
u0.wb_write(1, XGATE_XGIF_4, 16'hffff);
|
host.wb_write(1, XGATE_XGIF_4, 16'hffff, WORD);
|
if (79 < chan_val < 96)
|
if (79 < chan_val < 96)
|
u0.wb_write(1, XGATE_XGIF_5, 16'hffff);
|
host.wb_write(1, XGATE_XGIF_5, 16'hffff, WORD);
|
if (95 < chan_val < 112)
|
if (95 < chan_val < 112)
|
u0.wb_write(1, XGATE_XGIF_6, 16'hffff);
|
host.wb_write(1, XGATE_XGIF_6, 16'hffff, WORD);
|
if (111 < chan_val < 128)
|
if (111 < chan_val < 128)
|
u0.wb_write(1, XGATE_XGIF_7, 16'hffff);
|
host.wb_write(1, XGATE_XGIF_7, 16'hffff, WORD);
|
|
|
channel_req[chan_val] = 1'b0; //
|
channel_req[chan_val] = 1'b0; //
|
repeat(1) @(posedge mstr_test_clk);
|
repeat(1) @(posedge mstr_test_clk);
|
end
|
end
|
endtask
|
endtask
|
|
|
|
|
|
////////////////////////////////////////////////////////////////////////////////
|
task activate_thread_sw;
|
task activate_thread_sw;
|
input [ 6:0] chan_val;
|
input [ 6:0] chan_val;
|
begin
|
begin
|
$display("Activating Sofrware Thread - Channel #%d", chan_val);
|
$display("Activating Sofrware Thread - Channel #%d", chan_val);
|
|
|
data_xgmctl = XGMCTL_XGEM | XGMCTL_XGE;
|
data_xgmctl = XGMCTL_XGEM | XGMCTL_XGE;
|
u0.wb_write(0, XGATE_XGMCTL, data_xgmctl); // Enable XGATE
|
host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD); // Enable XGATE
|
|
|
channel_req[chan_val] = 1'b1; //
|
channel_req[chan_val] = 1'b1; //
|
repeat(1) @(posedge mstr_test_clk);
|
repeat(1) @(posedge mstr_test_clk);
|
end
|
end
|
endtask
|
endtask
|
|
|
task dump_ram;
|
////////////////////////////////////////////////////////////////////////////////
|
input [15:0] start_address;
|
|
reg [15:0] dump_address;
|
|
integer i, j;
|
|
begin
|
|
$display("Dumping RAM - Starting Address #%h", start_address);
|
|
|
|
dump_address = start_address;
|
|
while (dump_address <= start_address + 16'h0080)
|
|
begin
|
|
$write("Address = %h", dump_address);
|
|
for (i = 0; i < 16; i = i + 1)
|
|
begin
|
|
$write(" %h", ram_8[dump_address]);
|
|
dump_address = dump_address + 1;
|
|
end
|
|
$write("\n");
|
|
end
|
|
|
|
end
|
|
endtask
|
|
|
|
task wrap_up;
|
task wrap_up;
|
begin
|
begin
|
test_num = test_num + 1;
|
test_num = test_num + 1;
|
repeat(10) @(posedge mstr_test_clk);
|
repeat(10) @(posedge mstr_test_clk);
|
$display("\nSimulation Finished!! - vector =%d", vector);
|
$display("\nSimulation Finished!! - vector =%d", vector);
|
| Line 873... |
Line 955... |
|
|
$finish;
|
$finish;
|
end
|
end
|
endtask
|
endtask
|
|
|
|
////////////////////////////////////////////////////////////////////////////////
|
function [15:0] four_2_16;
|
function [15:0] four_2_16;
|
input [3:0] vector;
|
input [3:0] vector;
|
begin
|
begin
|
case (vector)
|
case (vector)
|
4'h0 : four_2_16 = 16'b0000_0000_0000_0001;
|
4'h0 : four_2_16 = 16'b0000_0000_0000_0001;
|
| Line 899... |
Line 982... |
end
|
end
|
endfunction
|
endfunction
|
|
|
endmodule // tst_bench_top
|
endmodule // tst_bench_top
|
|
|
|
////////////////////////////////////////////////////////////////////////////////
|
|
////////////////////////////////////////////////////////////////////////////////
|
|
////////////////////////////////////////////////////////////////////////////////
|
|
module bus_arbitration #(parameter dwidth = 32,
|
|
parameter awidth = 32)
|
|
(
|
|
// System bus I/O
|
|
output sys_cyc,
|
|
output sys_stb,
|
|
output sys_we,
|
|
output [dwidth/8 -1:0] sys_sel,
|
|
output [awidth -1:0] sys_adr,
|
|
output [dwidth -1:0] sys_dout,
|
|
|
|
// Host bus I/O
|
|
output host_ack,
|
|
output [dwidth -1:0] host_dout,
|
|
input host_cyc,
|
|
input host_stb,
|
|
input host_we,
|
|
input [dwidth/8 -1:0] host_sel,
|
|
input [awidth -1:0] host_adr,
|
|
input [dwidth -1:0] host_din,
|
|
|
|
// Alternate Bus Master #1 Bus I/O
|
|
output alt1_ack,
|
|
output [dwidth -1:0] alt1_dout,
|
|
input alt1_cyc,
|
|
input alt1_stb,
|
|
input alt1_we,
|
|
input [dwidth/8 -1:0] alt1_sel,
|
|
input [awidth -1:0] alt1_adr,
|
|
input [dwidth -1:0] alt1_din,
|
|
|
|
// Slave #1 Bus I/O
|
|
output slv1_stb,
|
|
input slv1_ack,
|
|
input [dwidth -1:0] slv1_din,
|
|
|
|
// Slave #2 Bus I/O
|
|
output slv2_stb,
|
|
input slv2_ack,
|
|
input [dwidth -1:0] slv2_din,
|
|
|
|
// Miscellaneous
|
|
input host_clk,
|
|
input risc_clk,
|
|
input rst, // No Connect
|
|
input err, // No Connect
|
|
input rty // No Connect
|
|
);
|
|
|
|
//////////////////////////////////////////////////////////////////////////////
|
|
//
|
|
// Local Wires and Registers
|
|
//
|
|
wire host_lock; // Host has the slave bus
|
|
reg host_lock_ext; // Host lock extend, Hold the bus till the transaction complets
|
|
reg [3:0] host_cycle_cnt; // Used to count the cycle the host and break the lock if the risc needs access
|
|
|
|
wire risc_lock; // RISC has the slave bus
|
|
reg risc_lock_ext; // RISC lock extend, Hold the bus till the transaction complets
|
|
reg [3:0] risc_cycle_cnt; // Used to count the cycle the risc and break the lock if the host needs access
|
|
|
|
// Aribartration Logic for System Bus access
|
|
always @(posedge host_clk or negedge rst)
|
|
if (!rst)
|
|
host_lock_ext <= 1'b0;
|
|
else
|
|
host_lock_ext <= host_cyc && !host_ack;
|
|
|
|
always @(posedge host_clk or negedge rst)
|
|
if (!rst)
|
|
risc_lock_ext <= 1'b0;
|
|
else
|
|
risc_lock_ext <= alt1_cyc && !alt1_ack;
|
|
|
|
// Start counting cycles the host has the bus if the risc is also requesting the bus
|
|
always @(posedge host_clk or negedge rst)
|
|
if (!rst)
|
|
host_cycle_cnt <= 0;
|
|
else
|
|
host_cycle_cnt <= (host_lock && alt1_cyc) ? (host_cycle_cnt + 1'b1) : 0;
|
|
|
|
// Start counting cycles the risc has the bus if the host is also requesting the bus
|
|
always @(posedge host_clk or negedge rst)
|
|
if (!rst)
|
|
risc_cycle_cnt <= 0;
|
|
else
|
|
risc_cycle_cnt <= (risc_lock && host_cyc) ? (risc_cycle_cnt + 1'b1) : 0;
|
|
|
|
assign host_lock = ((host_cyc && !risc_lock_ext) || host_lock_ext) && (host_cycle_cnt < 5);
|
|
assign risc_lock = !host_lock;
|
|
|
|
wire alt1_master = !host_lock;
|
|
|
|
// Address decoding for different XGATE module instances
|
|
assign slv1_stb = sys_stb && ~sys_adr[6] && ~sys_adr[5] && ~|sys_adr[31:16];
|
|
wire slv3_stb = sys_stb && ~sys_adr[6] && sys_adr[5] && ~|sys_adr[31:16];
|
|
wire slv4_stb = sys_stb && sys_adr[6] && ~sys_adr[5] && ~|sys_adr[31:16];
|
|
wire slv5_stb = sys_stb && sys_adr[6] && sys_adr[5] && ~|sys_adr[31:16];
|
|
|
|
// Address decoding for Testbench access to RAM
|
|
assign slv2_stb = alt1_master ? (alt1_stb && sys_adr[16] && ~|sys_adr[31:17]) :
|
|
(host_stb && ~sys_adr[16] && sys_adr[17] && ~|sys_adr[31:18]);
|
|
|
|
|
|
// Create the Host Read Data Bus
|
|
assign host_dout = ({dwidth{slv1_stb}} & slv1_din) |
|
|
({dwidth{slv2_stb}} & slv2_din);
|
|
|
|
// Create the Alternate #1 Read Data Bus
|
|
assign alt1_dout = ({dwidth{slv1_stb}} & slv1_din) |
|
|
({dwidth{slv2_stb}} & slv2_din);
|
|
|
|
assign host_ack = host_lock && (slv1_ack || slv2_ack);
|
|
assign alt1_ack = risc_lock && (slv1_ack || slv2_ack);
|
|
|
|
|
|
// Mux for System Bus access
|
|
assign sys_cyc = alt1_cyc || host_cyc;
|
|
assign sys_stb = alt1_master ? alt1_stb : host_stb;
|
|
assign sys_we = alt1_master ? alt1_we : host_we;
|
|
assign sys_sel = alt1_master ? alt1_sel : host_sel;
|
|
assign sys_adr = alt1_master ? alt1_adr : host_adr;
|
|
assign sys_dout = alt1_master ? alt1_din : host_din;
|
|
|
|
endmodule // bus_arbitration
|
|
|
|
|
|
|
|
|
No newline at end of file
|
No newline at end of file
|
