| Line 43... |
Line 43... |
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module tst_bench_top();
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module tst_bench_top();
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parameter MAX_CHANNEL = 127; // Max XGATE Interrupt Channel Number
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parameter MAX_CHANNEL = 127; // Max XGATE Interrupt Channel Number
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parameter STOP_ON_ERROR = 1'b0;
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parameter STOP_ON_ERROR = 1'b0;
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parameter MAX_VECTOR = 2200;
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parameter MAX_VECTOR = 2300;
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parameter L_BYTE = 2'b01;
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parameter L_BYTE = 2'b01;
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parameter H_BYTE = 2'b10;
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parameter H_BYTE = 2'b10;
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parameter WORD = 2'b11;
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parameter WORD = 2'b11;
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| Line 237... |
Line 237... |
$display("\n ------ !!!!! Simulation Timeout at vector=%d\n -------", vector);
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$display("\n ------ !!!!! Simulation Timeout at vector=%d\n -------", vector);
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wrap_up;
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wrap_up;
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end
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end
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end
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end
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// Add up errors tha come from WISHBONE read compares
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// Add up errors that come from WISHBONE read compares
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always @host.cmp_error_detect
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always @host.cmp_error_detect
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begin
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begin
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error_count <= error_count + 1;
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error_count <= error_count + 1;
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end
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end
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// Throw in some wait states from the memory
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// Throw in some wait states from the memory
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always @(posedge mstr_test_clk)
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always @(posedge mstr_test_clk)
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if (((vector % 5) == 0) && (xgate.risc.load_next_inst || xgate.risc.data_access))
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if (((vector % 5) == 0) && (xgate.risc.load_next_inst || xgate.risc.data_access))
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// if ((vector % 5) == 0)
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// if ((vector % 5) == 0)
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wbm_ack_i <= 1'b0;
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wbm_ack_i <= 1'b1;
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else
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else
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wbm_ack_i <= 1'b1;
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wbm_ack_i <= 1'b1;
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// Special Memory Mapped Testbench Registers
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// Special Memory Mapped Testbench Registers
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| Line 788... |
Line 788... |
read_ram_cmp(16'h0068,16'h2fcc);
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read_ram_cmp(16'h0068,16'h2fcc);
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read_ram_cmp(16'h0022,16'hccxx);
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read_ram_cmp(16'h0022,16'hccxx);
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read_ram_cmp(16'h0026,16'hxx99);
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read_ram_cmp(16'h0026,16'hxx99);
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read_ram_cmp(16'h0052,16'hxx66);
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read_ram_cmp(16'h0052,16'hxx66);
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read_ram_cmp(16'h0058,16'h99xx);
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read_ram_cmp(16'h0058,16'h99xx);
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data_xgmctl = 16'hff00;
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host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD); // Disable XGATE
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end
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end
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endtask
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endtask
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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// check register bits - reset, read/write
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// check register bits - reset, read/write
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| Line 1107... |
Line 1111... |
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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task activate_thread_sw;
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task activate_thread_sw;
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input [ 6:0] chan_val;
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input [ 6:0] chan_val;
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begin
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begin
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$display("Activating Sofrware Thread - Channel #%d", chan_val);
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$display("Activating Software Thread - Channel #%d", chan_val);
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data_xgmctl = XGMCTL_XGEM | XGMCTL_XGE;
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data_xgmctl = XGMCTL_XGEM | XGMCTL_XGE;
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host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD); // Enable XGATE
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host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD); // Enable XGATE
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channel_req[chan_val] = 1'b1; //
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channel_req[chan_val] = 1'b1; //
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