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Line 43... |
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module tst_bench_top();
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module tst_bench_top();
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parameter MAX_CHANNEL = 127; // Max XGATE Interrupt Channel Number
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parameter MAX_CHANNEL = 127; // Max XGATE Interrupt Channel Number
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parameter STOP_ON_ERROR = 1'b0;
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parameter STOP_ON_ERROR = 1'b0;
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parameter MAX_VECTOR = 3000;
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parameter MAX_VECTOR = 8000;
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parameter L_BYTE = 2'b01;
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parameter L_BYTE = 2'b01;
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parameter H_BYTE = 2'b10;
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parameter H_BYTE = 2'b10;
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parameter WORD = 2'b11;
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parameter WORD = 2'b11;
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Line 1193... |
input rst, // No Connect
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input rst, // No Connect
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input err, // No Connect
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input err, // No Connect
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input rty // No Connect
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input rty // No Connect
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);
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);
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// Debug states for change CHID
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// States for bus arbitration
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parameter [1:0] BUS_IDLE = 2'b00,
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parameter [1:0] BUS_IDLE = 2'b00,
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HOST_OWNS = 2'b10,
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HOST_OWNS = 2'b10,
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RISC_OWNS = 2'b11;
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RISC_OWNS = 2'b11;
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parameter max_bus_hold = 5; // Max number of cycles any bus master can hold the system bus
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parameter ram_wait_states = 0; // Number between 0 and 15
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//////////////////////////////////////////////////////////////////////////////
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//////////////////////////////////////////////////////////////////////////////
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//
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//
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// Local Wires and Registers
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// Local Wires and Registers
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//
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//
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wire ram_ack; //
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wire ram_ack; //
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Line 1219... |
reg [1:0] owner_ns;
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reg [1:0] owner_ns;
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wire host_timeout;
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wire host_timeout;
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wire risc_timeout;
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wire risc_timeout;
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reg wbm_ack_i;
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wire ram_ack_dly; // Delayed bus ack to simulate bus wait states
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reg [3:0] ack_dly_cnt; // Counter to delay bus ack to master modules
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//
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//
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always @(posedge host_clk or negedge rst)
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always @(posedge host_clk or negedge rst)
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if (!rst)
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if (!rst)
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owner_ns = HOST_OWNS;
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owner_ns = HOST_OWNS;
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end
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end
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default : owner_ns = BUS_IDLE;
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default : owner_ns = BUS_IDLE;
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endcase
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endcase
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/*
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// Throw in some wait states from the memory
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always @(posedge mstr_test_clk)
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if (((vector % 5) == 0) && (xgate.risc.load_next_inst || xgate.risc.data_access))
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// if ((vector % 5) == 0)
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wbm_ack_i <= 1'b1;
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else
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wbm_ack_i <= 1'b1;
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*/
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assign host_timeout = (owner_state == HOST_OWNS) && (host_cycle_cnt > max_bus_hold) && any_ack;
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assign host_timeout = (owner_state == HOST_OWNS) && (host_cycle_cnt > 5) && any_ack;
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assign risc_timeout = (owner_state == RISC_OWNS) && (risc_cycle_cnt > max_bus_hold) && any_ack;
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assign risc_timeout = (owner_state == RISC_OWNS) && (risc_cycle_cnt > 5) && any_ack;
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// Start counting cycles that the host has the bus, if the risc is also requesting the bus
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// Start counting cycles that the host has the bus, if the risc is also requesting the bus
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always @(posedge host_clk or negedge rst)
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always @(posedge host_clk or negedge rst)
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if (!rst)
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if (!rst)
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host_cycle_cnt <= 0;
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host_cycle_cnt <= 0;
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// Address decoding for Testbench access to RAM
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// Address decoding for Testbench access to RAM
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assign ram_sel = sys_cyc && sys_stb && !(slv1_stb || slv2_stb) &&
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assign ram_sel = sys_cyc && sys_stb && !(slv1_stb || slv2_stb) &&
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(sys_adr >= ram_base) &&
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(sys_adr >= ram_base) &&
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(sys_adr < (ram_base + ram_size));
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(sys_adr < (ram_base + ram_size));
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assign ram_ack = ram_sel;
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// Throw in some wait states from the memory
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always @(posedge host_clk)
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if ((ack_dly_cnt == ram_wait_states) || !ram_sel)
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ack_dly_cnt <= 0;
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else if (ram_sel)
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ack_dly_cnt <= ack_dly_cnt + 1'b1;
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assign ram_ack_dly = (ack_dly_cnt == ram_wait_states);
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assign ram_ack = ram_sel && ram_ack_dly;
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// Create the System Read Data Bus from the Slave output data buses
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// Create the System Read Data Bus from the Slave output data buses
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assign sys_din = ({dwidth{slv1_stb}} & slv1_din) |
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assign sys_din = ({dwidth{slv1_stb}} & slv1_din) |
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({dwidth{slv2_stb}} & slv2_din) |
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({dwidth{slv2_stb}} & slv2_din) |
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