| Line 101... |
Line 101... |
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parameter CHECK_POINT = 16'h8000;
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parameter CHECK_POINT = 16'h8000;
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parameter CHANNEL_ACK = CHECK_POINT + 2;
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parameter CHANNEL_ACK = CHECK_POINT + 2;
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parameter CHANNEL_ERR = CHECK_POINT + 4;
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parameter CHANNEL_ERR = CHECK_POINT + 4;
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parameter SYS_RAM_BASE = 24'h0000_0000;
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parameter SYS_RAM_BASE = 24'h00_0000;
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//
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//
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// wires && regs
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// wires && regs
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//
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//
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reg mstr_test_clk;
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reg mstr_test_clk;
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| Line 116... |
Line 116... |
reg [15:0] q, qq;
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reg [15:0] q, qq;
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reg rstn;
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reg rstn;
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reg sync_reset;
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reg sync_reset;
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reg por_reset_b;
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reg por_reset_b;
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reg stop_mode;
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reg wait_mode;
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reg debug_mode;
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reg scantestmode;
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reg scantestmode;
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wire [15:0] dat_i;
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wire ack;
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reg [MAX_CHANNEL:0] channel_req; // XGATE Interrupt inputs
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reg [MAX_CHANNEL:0] channel_req; // XGATE Interrupt inputs
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wire [MAX_CHANNEL:0] xgif; // XGATE Interrupt outputs
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wire [MAX_CHANNEL:0] xgif; // XGATE Interrupt outputs
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wire [ 7:0] xgswt; // XGATE Software Trigger outputs
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wire [ 7:0] xgswt; // XGATE Software Trigger outputs
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wire xg_sw_irq; // Xgate Software Error interrupt
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wire xg_sw_irq; // Xgate Software Error interrupt
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| Line 139... |
Line 133... |
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reg mem_wait_state_enable;
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reg mem_wait_state_enable;
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wire [15:0] tb_ram_out;
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wire [15:0] tb_ram_out;
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wire [15:0] tb_slave_dout; // WISHBONE data bus output from testbench slave module
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wire error_pulse; // Error detected output pulse from the testbench slave module
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wire test_reg_ack; // WISHBONE ack from testbench slave module
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wire ack_pulse; // Thread ack output pulse from testbench slave module
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wire wbm_cyc_o;
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wire wbm_stb_o;
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wire wbm_we_o;
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wire wbs_err_o;
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// Registers used to mirror internal registers
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// Registers used to mirror internal registers
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reg [15:0] data_xgmctl;
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reg [15:0] data_xgmctl;
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reg [15:0] data_xgchid;
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reg [15:0] data_xgchid;
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reg [15:0] data_xgvbr;
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reg [15:0] data_xgvbr;
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reg [15:0] data_xgswt;
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reg [15:0] data_xgswt;
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| Line 187... |
Line 192... |
begin
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begin
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mstr_test_clk = 0;
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mstr_test_clk = 0;
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vector = 0;
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vector = 0;
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test_num = 0;
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test_num = 0;
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por_reset_b = 0;
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por_reset_b = 0;
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stop_mode = 0;
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wait_mode = 0;
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debug_mode = 0;
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scantestmode = 0;
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scantestmode = 0;
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error_count = 0;
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error_count = 0;
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mem_wait_state_enable = 0;
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mem_wait_state_enable = 0;
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// channel_req = 0;
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// channel_req = 0;
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| Line 322... |
Line 324... |
.slv1_ack( xgate_s_ack ),
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.slv1_ack( xgate_s_ack ),
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.slv1_din( xgate_s_dout ),
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.slv1_din( xgate_s_dout ),
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// Slave #2 Bus I/O
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// Slave #2 Bus I/O
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.slv2_stb( slv2_stb ),
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.slv2_stb( slv2_stb ),
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.slv2_ack( test_reg_ack ),
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.slv2_ack( test_reg_ack ),
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.slv2_din( ram_dout ),
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.slv2_din( tb_slave_dout ),
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// Miscellaneous
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// Miscellaneous
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.host_clk( mstr_test_clk ),
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.host_clk( mstr_test_clk ),
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.risc_clk( mstr_test_clk ),
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.risc_clk( mstr_test_clk ),
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.rst( rstn ), // No Connect
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.rst( rstn ), // No Connect
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.err( 1'b0 ), // No Connect
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.err( 1'b0 ), // No Connect
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| Line 364... |
Line 366... |
.xgif( xgif ), // XGATE Interrupt Flag output
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.xgif( xgif ), // XGATE Interrupt Flag output
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.xg_sw_irq( xg_sw_irq ), // XGATE Software Error Interrupt Flag output
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.xg_sw_irq( xg_sw_irq ), // XGATE Software Error Interrupt Flag output
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.xgswt( xgswt ),
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.xgswt( xgswt ),
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.risc_clk( mstr_test_clk ),
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.risc_clk( mstr_test_clk ),
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.chan_req_i( {channel_req[MAX_CHANNEL:40], xgswt, channel_req[31:0]} ),
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.chan_req_i( {channel_req[MAX_CHANNEL:40], xgswt, channel_req[31:0]} ),
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.debug_mode_i( 1'b0 ),
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.secure_mode_i( 1'b0 ),
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.scantestmode( scantestmode )
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.scantestmode( scantestmode )
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);
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);
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|
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tb_slave #(.DWIDTH(16),
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tb_slave #(.DWIDTH(16),
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.SINGLE_CYCLE(1'b1))
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.SINGLE_CYCLE(1'b1))
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| Line 376... |
Line 380... |
.wb_clk_i( mstr_test_clk ),
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.wb_clk_i( mstr_test_clk ),
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.wb_rst_i( 1'b0 ),
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.wb_rst_i( 1'b0 ),
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.arst_i( rstn ),
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.arst_i( rstn ),
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.wb_adr_i( sys_adr[3:1] ),
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.wb_adr_i( sys_adr[3:1] ),
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.wb_dat_i( sys_dout ),
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.wb_dat_i( sys_dout ),
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.wb_dat_o(),
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.wb_dat_o( tb_slave_dout),
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.wb_we_i( sys_we ),
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.wb_we_i( sys_we ),
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.wb_stb_i( slv2_stb ),
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.wb_stb_i( slv2_stb ),
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.wb_cyc_i( sys_cyc ),
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.wb_cyc_i( sys_cyc ),
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.wb_sel_i( sys_sel ),
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.wb_sel_i( sys_sel ),
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.wb_ack_o( test_reg_ack ),
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.wb_ack_o( test_reg_ack ),
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| Line 1375... |
Line 1379... |
input [DWIDTH-1:0] wb_dat_i, // databus input
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input [DWIDTH-1:0] wb_dat_i, // databus input
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input wb_we_i, // write enable input
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input wb_we_i, // write enable input
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input wb_stb_i, // stobe/core select signal
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input wb_stb_i, // stobe/core select signal
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input wb_cyc_i, // valid bus cycle input
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input wb_cyc_i, // valid bus cycle input
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input [1:0] wb_sel_i, // Select byte in word bus transaction
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input [1:0] wb_sel_i, // Select byte in word bus transaction
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// PIT IO Signals
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// Slave unique IO Signals
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output reg error_pulse, // Error detected output pulse
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output reg error_pulse, // Error detected output pulse
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output reg ack_pulse, // Thread ack output pulse
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output reg ack_pulse, // Thread ack output pulse
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input [19:0] vector
|
input [19:0] vector
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);
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);
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|
|
