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[/] [xgate/] [trunk/] [bench/] [verilog/] [tst_bench_top.v] - Diff between revs 62 and 65

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Rev 62 Rev 65
Line 43... Line 43... 
 
 
 
 
module tst_bench_top();
 
module tst_bench_top();
 
 
 
 
 
  parameter MAX_CHANNEL = 127;    // Max XGATE Interrupt Channel Number
 
  parameter MAX_CHANNEL = 127;    // Max XGATE Interrupt Channel Number
 
  parameter STOP_ON_ERROR = 1'b0;
 
  parameter STOP_ON_ERROR = 1'b0;
 
  parameter MAX_VECTOR = 8000;
 
  parameter MAX_VECTOR = 9000;
 
 
 
 
 
  parameter L_BYTE = 2'b01;
 
  parameter L_BYTE = 2'b01;
 
  parameter H_BYTE = 2'b10;
 
  parameter H_BYTE = 2'b10;
 
  parameter WORD   = 2'b11;
 
  parameter WORD   = 2'b11;
 
 
 
 
Line 103... Line 103... 
  parameter CHANNEL_ACK = CHECK_POINT + 2;
 
  parameter CHANNEL_ACK = CHECK_POINT + 2;
 
  parameter CHANNEL_ERR = CHECK_POINT + 4;
 
  parameter CHANNEL_ERR = CHECK_POINT + 4;
 
 
 
 
 
  parameter SYS_RAM_BASE = 24'h00_0000;
 
  parameter SYS_RAM_BASE = 24'h00_0000;
 
 
 
 
 
 
 
  parameter RAM_WAIT_STATES = 0; // Number between 0 and 15
 
 
 
  parameter SYS_READ_DELAY = 10;
 
 
 
  parameter XGATE_ACCESS_DELAY = SYS_READ_DELAY + RAM_WAIT_STATES;
 
 
 
  parameter XGATE_SS_DELAY = XGATE_ACCESS_DELAY + RAM_WAIT_STATES;
 
 
 
 
 
 
 
 
 
  //
 
  //
 
  // wires && regs
 
  // wires && regs
 
  //
 
  //
 
  reg         mstr_test_clk;
 
  reg         mstr_test_clk;
 
  reg  [19:0] vector;
 
  reg  [19:0] vector;
Line 287... Line 293... 
                     .ram_base(0),
 
                     .ram_base(0),
 
                     .ram_size(17'h10000),
 
                     .ram_size(17'h10000),
 
                     .slv1_base(XGATE_BASE),
 
                     .slv1_base(XGATE_BASE),
 
                     .slv1_size(64),
 
                     .slv1_size(64),
 
                     .slv2_base(CHECK_POINT),
 
                     .slv2_base(CHECK_POINT),
 
                     .slv2_size(8))
 
                     .slv2_size(8),
 
 
 
                     .ram_wait_states(RAM_WAIT_STATES)
 
 
 
)
 
    arb(
 
    arb(
 
    // System bus I/O
 
    // System bus I/O
 
    .sys_cyc( sys_cyc ),
 
    .sys_cyc( sys_cyc ),
 
    .sys_stb( sys_stb ),
 
    .sys_stb( sys_stb ),
 
    .sys_we( sys_we ),
 
    .sys_we( sys_we ),
Line 389... Line 397... 
          .wb_sel_i( sys_sel ),
 
          .wb_sel_i( sys_sel ),
 
          .wb_ack_o( test_reg_ack ),
 
          .wb_ack_o( test_reg_ack ),
 
 
 
 
 
          .ack_pulse( ack_pulse ),
 
          .ack_pulse( ack_pulse ),
 
          .error_pulse( error_pulse ),
 
          .error_pulse( error_pulse ),
 
 
 
          .brk_pt(  ),
 
 
 
          .x_address( wbm_adr_o ),
 
          .vector( vector )
 
          .vector( vector )
 
  );
 
  );
 
 
 
 
 
 
 
 
 
 
 
 
Line 446... Line 456... 
    $display("\nTEST #%d Starts at vector=%d, test_chid_debug", test_num, vector);
 
    $display("\nTEST #%d Starts at vector=%d, test_chid_debug", test_num, vector);
 
    $readmemh("../../../bench/verilog/debug_test.v", p_ram.ram_8);
 
    $readmemh("../../../bench/verilog/debug_test.v", p_ram.ram_8);
 
 
 
 
 
    data_xgmctl = XGMCTL_XGBRKIEM | XGMCTL_XGBRKIE;
 
    data_xgmctl = XGMCTL_XGBRKIEM | XGMCTL_XGBRKIE;
 
    host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD);    // Enable interrupt on BRK instruction
 
    host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD);    // Enable interrupt on BRK instruction
 
 
 
    $display("BRK Software Error Interrupt enabled at vector=%d", vector);
 
 
 
 
 
    activate_thread_sw(3);
 
    activate_thread_sw(3);
 
 
 
 
 
    wait_debug_set;   // Debug Status bit is set by BRK instruction
 
    wait_debug_set;   // Debug Status bit is set by BRK instruction
 
 
 
 
 
    host.wb_cmp(0, XGATE_XGPC,      16'h20c6, WORD);      // See Program code (BRK).
 
    host.wb_cmp(0, XGATE_XGPC,      16'h20c6, WORD);      // See Program code (BRK).
 
    host.wb_cmp(0, XGATE_XGR3,      16'h0001, WORD);      // See Program code.R3 = 1
 
    host.wb_cmp(0, XGATE_XGR3,      16'h0001, WORD);      // See Program code.R3 = 1
 
    host.wb_cmp(0, XGATE_XGCHID,   16'h0003, WORD);       // Check for Correct CHID
 
    host.wb_cmp(0, XGATE_XGCHID,   16'h0003, WORD);       // Check for Correct CHID
 
 
 
    $display("Debug entry detected at vector=%d", vector);
 
 
 
 
 
    channel_req[5] = 1'b1; //
 
    channel_req[5] = 1'b1; //
 
    repeat(7) @(posedge mstr_test_clk);
 
    repeat(7) @(posedge mstr_test_clk);
 
    host.wb_cmp(0, XGATE_XGCHID,   16'h0003, WORD);       // Check for Correct CHID
 
    host.wb_cmp(0, XGATE_XGCHID,   16'h0003, WORD);       // Check for Correct CHID
 
 
 
 
Line 473... Line 485... 
    repeat(1) @(posedge mstr_test_clk);
 
    repeat(1) @(posedge mstr_test_clk);
 
 
 
 
 
    host.wb_write(0, XGATE_XGCHID, 16'h0004, WORD);       // Change CHID
 
    host.wb_write(0, XGATE_XGCHID, 16'h0004, WORD);       // Change CHID
 
 
 
 
 
    repeat(8) @(posedge mstr_test_clk);
 
    repeat(8) @(posedge mstr_test_clk);
 
 
 
    $display("Channel ID changed at vector=%d", vector);
 
 
 
 
 
 
 
 
 
    data_xgmctl = XGMCTL_XGDBGM;
 
    data_xgmctl = XGMCTL_XGDBGM;
 
    host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD);    // Clear Debug Mode Control Bit
 
    host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD);    // Clear Debug Mode Control Bit
 
 
 
 
 
    wait_debug_set;   // Debug Status bit is set by BRK instruction
 
    wait_debug_set;   // Debug Status bit is set by BRK instruction
Line 491... Line 505... 
    wait_debug_set;   // Debug Status bit is set by BRK instruction
 
    wait_debug_set;   // Debug Status bit is set by BRK instruction
 
    host.wb_cmp(0, XGATE_XGCHID,   16'h0006, WORD);       // Check for Correct CHID
 
    host.wb_cmp(0, XGATE_XGCHID,   16'h0006, WORD);       // Check for Correct CHID
 
    host.wb_cmp(0, XGATE_XGPC,      16'h211c, WORD);      // See Program code (BRK)
 
    host.wb_cmp(0, XGATE_XGPC,      16'h211c, WORD);      // See Program code (BRK)
 
    data_xgmctl = XGMCTL_XGSSM | XGMCTL_XGSS;
 
    data_xgmctl = XGMCTL_XGSSM | XGMCTL_XGSS;
 
    host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD);    // Do a Single Step
 
    host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD);    // Do a Single Step
 
    repeat(8) @(posedge mstr_test_clk);
 
    repeat(XGATE_SS_DELAY) @(posedge mstr_test_clk);
 
    host.wb_cmp(0, XGATE_XGPC,      16'h211e, WORD);      // See Program code (BRA)
 
    host.wb_cmp(0, XGATE_XGPC,      16'h211e, WORD);      // See Program code (BRA)
 
    host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD);    // Do a Single Step
 
    host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD);    // Do a Single Step
 
    repeat(8) @(posedge mstr_test_clk);
 
    repeat(XGATE_SS_DELAY) @(posedge mstr_test_clk);
 
    host.wb_cmp(0, XGATE_XGPC,      16'h2122, WORD);      // See Program code ()
 
    host.wb_cmp(0, XGATE_XGPC,      16'h2122, WORD);      // See Program code ()
 
 
 
 
 
    repeat(20) @(posedge mstr_test_clk);
 
    repeat(20) @(posedge mstr_test_clk);
 
 
 
 
 
    data_xgmctl = XGMCTL_XGDBGM;
 
    data_xgmctl = XGMCTL_XGDBGM;
Line 539... Line 553... 
    data_xgmctl = XGMCTL_XGBRKIEM | XGMCTL_XGBRKIE;
 
    data_xgmctl = XGMCTL_XGBRKIEM | XGMCTL_XGBRKIE;
 
    host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD);    // Enable interrupt on BRK instruction
 
    host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD);    // Enable interrupt on BRK instruction
 
 
 
 
 
    activate_thread_sw(2);
 
    activate_thread_sw(2);
 
 
 
 
 
    repeat(25) @(posedge mstr_test_clk);
 
    // Approxmatly 12 instructions need to be done before activating Debug Mode
 
 
 
    repeat(12 + RAM_WAIT_STATES*12) @(posedge mstr_test_clk);
 
 
 
 
 
    data_xgmctl = XGMCTL_XGDBGM | XGMCTL_XGDBG;
 
    data_xgmctl = XGMCTL_XGDBGM | XGMCTL_XGDBG;
 
    host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD);    // Set Debug Mode Control Bit
 
    host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD);    // Set Debug Mode Control Bit
 
    repeat(5) @(posedge mstr_test_clk);
 
    repeat(5) @(posedge mstr_test_clk);
 
 
 
    $display("DEBUG bit set at vector=%d", vector);
 
 
 
 
 
    host.wb_read(1, XGATE_XGR3, q, WORD);
 
    host.wb_read(1, XGATE_XGR3, q, WORD);
 
    data_xgmctl = XGMCTL_XGSSM | XGMCTL_XGSS;
 
    data_xgmctl = XGMCTL_XGSSM | XGMCTL_XGSS;
 
    qq = q;
 
    qq = q;
 
 
 
 
 
    // The Xgate test program is in an infinate loop incrementing R3
 
    // The Xgate test program is in an infinate loop incrementing R3
 
    while (qq == q)  // Look for change in R3 register
 
    while (qq == q)  // Look for change in R3 register
 
      begin
 
      begin
 
        host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD);   // Do a Single Step
 
        host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD);   // Do a Single Step
 
        repeat(7) @(posedge mstr_test_clk);
 
        repeat(XGATE_SS_DELAY) @(posedge mstr_test_clk);
 
        host.wb_read(1, XGATE_XGR3, q, WORD);
 
        host.wb_read(1, XGATE_XGR3, q, WORD);
 
      end
 
      end
 
    if (q != (qq+1))
 
    if (q != (qq+1))
 
      begin
 
      begin
 
        $display("Error! - Unexpected value of R3 at vector=%d", vector);
 
        $display("Error! - Unexpected value of R3 at vector=%d", vector);
Line 565... Line 581... 
      end
 
      end
 
 
 
 
 
 
 
 
 
    host.wb_write(1, XGATE_XGPC, 16'h2094, WORD);        // Write to PC to force exit from infinite loop
 
    host.wb_write(1, XGATE_XGPC, 16'h2094, WORD);        // Write to PC to force exit from infinite loop
 
    repeat(10) @(posedge mstr_test_clk);
 
    repeat(10) @(posedge mstr_test_clk);
 
 
 
    host.wb_cmp(0, XGATE_XGPC,      16'h2094, WORD);      // Verify Proram Counter was changed
 
 
 
    $display("Program Counter changed at vector=%d", vector);
 
 
 
 
 
    data_xgmctl = XGMCTL_XGSSM | XGMCTL_XGSS;
 
    data_xgmctl = XGMCTL_XGSSM | XGMCTL_XGSS;
 
    host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD);    // Do a Single Step (Load ADDL instruction)
 
    host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD);    // Do a Single Step (Load ADDL instruction)
 
    repeat(10) @(posedge mstr_test_clk);
 
    repeat(XGATE_SS_DELAY) @(posedge mstr_test_clk);
 
    host.wb_cmp(0, XGATE_XGR4,      16'h0002, WORD);      // See Program code.(R4 <= R4 + 1)
 
    host.wb_cmp(0, XGATE_XGR4,      16'h0002, WORD);      // See Program code.(R4 <= R4 + 1)
 
 
 
 
 
    host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD);    // Do a Single Step (Load ADDL instruction)
 
    host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD);    // Do a Single Step (Load ADDL instruction)
 
    repeat(10) @(posedge mstr_test_clk);
 
    repeat(XGATE_SS_DELAY) @(posedge mstr_test_clk);
 
    host.wb_cmp(0, XGATE_XGR4,      16'h0003, WORD);      // See Program code.(R4 <= R4 + 1)
 
    host.wb_cmp(0, XGATE_XGR4,      16'h0003, WORD);      // See Program code.(R4 <= R4 + 1)
 
 
 
 
 
    data_xgmctl = XGMCTL_XGDBGM;
 
    data_xgmctl = XGMCTL_XGDBGM;
 
    host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD);    // Clear Debug Mode Control Bit
 
    host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD);    // Clear Debug Mode Control Bit
 
                                                 // Should be back in Run Mode
 
                                                 // Should be back in Run Mode
Line 607... Line 625... 
    host.wb_cmp(0, XGATE_XGR3,      16'h0001, WORD);      // See Program code.R3 = 1
 
    host.wb_cmp(0, XGATE_XGR3,      16'h0001, WORD);      // See Program code.R3 = 1
 
 
 
 
 
    data_xgmctl = XGMCTL_XGSSM | XGMCTL_XGSS;
 
    data_xgmctl = XGMCTL_XGSSM | XGMCTL_XGSS;
 
 
 
 
 
    host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD);    // Do a Single Step (Load ADDL instruction)
 
    host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD);    // Do a Single Step (Load ADDL instruction)
 
    repeat(5) @(posedge mstr_test_clk);
 
    repeat(XGATE_SS_DELAY) @(posedge mstr_test_clk);
 
    host.wb_cmp(0, XGATE_XGPC,      16'h203c, WORD);      // PC + 2.
 
    host.wb_cmp(0, XGATE_XGPC,      16'h203c, WORD);      // PC + 2.
 
 
 
 
 
    host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD);    // Do a Single Step (Load NOP instruction)
 
    host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD);    // Do a Single Step (Load NOP instruction)
 
    repeat(5) @(posedge mstr_test_clk);                  // Execute ADDL instruction
 
    repeat(XGATE_SS_DELAY) @(posedge mstr_test_clk);                     // Execute ADDL instruction
 
    host.wb_cmp(0, XGATE_XGR3,      16'h0002, WORD);      // See Program code.(R3 <= R3 + 1)
 
    host.wb_cmp(0, XGATE_XGR3,      16'h0002, WORD);      // See Program code.(R3 <= R3 + 1)
 
    host.wb_cmp(0, XGATE_XGCCR,     16'h0000, WORD);      // See Program code.
 
    host.wb_cmp(0, XGATE_XGCCR,     16'h0000, WORD);      // See Program code.
 
    host.wb_cmp(0, XGATE_XGPC,      16'h203e, WORD);      // PC + 2.
 
    host.wb_cmp(0, XGATE_XGPC,      16'h203e, WORD);      // PC + 2.
 
    repeat(5) @(posedge mstr_test_clk);
 
    repeat(XGATE_SS_DELAY) @(posedge mstr_test_clk);
 
    host.wb_cmp(0, XGATE_XGPC,      16'h203e, WORD);      // Still no change.
 
    host.wb_cmp(0, XGATE_XGPC,      16'h203e, WORD);      // Still no change.
 
 
 
 
 
    host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD);    // Do a Single Step (Load BRA instruction)
 
    host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD);    // Do a Single Step (Load BRA instruction)
 
    repeat(9) @(posedge mstr_test_clk);                  // Execute NOP instruction
 
    repeat(XGATE_SS_DELAY) @(posedge mstr_test_clk);                     // Execute NOP instruction
 
    host.wb_cmp(0, XGATE_XGPC,      16'h2040, WORD);      // See Program code.
 
    host.wb_cmp(0, XGATE_XGPC,      16'h2040, WORD);      // See Program code.
 
 
 
 
 
 
 
 
 
    host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD);    // Do a Single Step
 
    host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD);    // Do a Single Step
 
    repeat(5) @(posedge mstr_test_clk);                  // Execute BRA instruction
 
    repeat(XGATE_SS_DELAY) @(posedge mstr_test_clk);                     // Execute BRA instruction
 
    host.wb_cmp(0, XGATE_XGPC,      16'h2064, WORD);      // PC = Branch destination.
 
    host.wb_cmp(0, XGATE_XGPC,      16'h2064, WORD);      // PC = Branch destination.
 
                                                         // Load ADDL instruction
 
                                                         // Load ADDL instruction
 
 
 
 
 
    host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD);    // Do a Single Step (Load LDW R7 instruction)
 
    host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD);    // Do a Single Step (Load LDW R7 instruction)
 
    repeat(5) @(posedge mstr_test_clk);                  // Execute ADDL instruction
 
    repeat(XGATE_SS_DELAY) @(posedge mstr_test_clk);                     // Execute ADDL instruction
 
    host.wb_cmp(0, XGATE_XGPC,      16'h2066, WORD);      // PC + 2.
 
    host.wb_cmp(0, XGATE_XGPC,      16'h2066, WORD);      // PC + 2.
 
    host.wb_cmp(0, XGATE_XGR3,      16'h0003, WORD);      // See Program code.(R3 <= R3 + 1)
 
    host.wb_cmp(0, XGATE_XGR3,      16'h0003, WORD);      // See Program code.(R3 <= R3 + 1)
 
 
 
 
 
    host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD);    // Do a Single Step (LDW R7)
 
    host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD);    // Do a Single Step (LDW R7)
 
    repeat(5) @(posedge mstr_test_clk);
 
    repeat(XGATE_SS_DELAY) @(posedge mstr_test_clk);
 
    host.wb_cmp(0, XGATE_XGPC,      16'h2068, WORD);      // PC + 2.
 
    host.wb_cmp(0, XGATE_XGPC,      16'h2068, WORD);      // PC + 2.
 
    host.wb_cmp(0, XGATE_XGR7,      16'h00c3, WORD);      // See Program code
 
    host.wb_cmp(0, XGATE_XGR7,      16'h00c3, WORD);      // See Program code
 
 
 
 
 
    repeat(1) @(posedge mstr_test_clk);
 
    repeat(1) @(posedge mstr_test_clk);
 
    host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD);    // Do a Single Step (BRA)
 
    host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD);    // Do a Single Step (BRA)
 
    repeat(9) @(posedge mstr_test_clk);
 
    repeat(XGATE_SS_DELAY) @(posedge mstr_test_clk);
 
    host.wb_cmp(0, XGATE_XGPC,      16'h2048, WORD);      // See Program code.
 
    host.wb_cmp(0, XGATE_XGPC,      16'h2048, WORD);      // See Program code.
 
 
 
 
 
    host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD);    // Do a Single Step (STW R3)
 
    host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD);    // Do a Single Step (STW R3)
 
    repeat(5) @(posedge mstr_test_clk);
 
    repeat(XGATE_SS_DELAY) @(posedge mstr_test_clk);
 
    host.wb_cmp(0, XGATE_XGPC,      16'h204a, WORD);      // PC + 2.
 
    host.wb_cmp(0, XGATE_XGPC,      16'h204a, WORD);      // PC + 2.
 
    host.wb_cmp(0, XGATE_XGR3,      16'h0003, WORD);      // See Program code.(R3 <= R3 + 1)
 
    host.wb_cmp(0, XGATE_XGR3,      16'h0003, WORD);      // See Program code.(R3 <= R3 + 1)
 
 
 
 
 
    host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD);    // Do a Single Step (R3 <= R3 + 1)
 
    host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD);    // Do a Single Step (R3 <= R3 + 1)
 
    repeat(5) @(posedge mstr_test_clk);
 
    repeat(XGATE_SS_DELAY) @(posedge mstr_test_clk);
 
    host.wb_cmp(0, XGATE_XGPC,      16'h204c, WORD);      // PC + 2.
 
    host.wb_cmp(0, XGATE_XGPC,      16'h204c, WORD);      // PC + 2.
 
 
 
 
 
    repeat(5) @(posedge mstr_test_clk);
 
    repeat(XGATE_SS_DELAY) @(posedge mstr_test_clk);
 
 
 
 
 
    data_xgmctl = XGMCTL_XGDBGM;
 
    data_xgmctl = XGMCTL_XGDBGM;
 
    host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD);    // Clear Debug Mode Control Bit
 
    host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD);    // Clear Debug Mode Control Bit
 
                                                         // Should be back in Run Mode
 
                                                         // Should be back in Run Mode
 
    wait_irq_set(1);
 
    wait_irq_set(1);
Line 673... Line 691... 
// Test instruction set
 
// Test instruction set
 
task test_inst_set;
 
task test_inst_set;
 
  begin
 
  begin
 
    $readmemh("../../../bench/verilog/inst_test.v", p_ram.ram_8);
 
    $readmemh("../../../bench/verilog/inst_test.v", p_ram.ram_8);
 
    test_num = test_num + 1;
 
    test_num = test_num + 1;
 
    $display("\nTEST #%d Starts at vector=%d, inst_test", test_num, vector);
 
    $display("\nTEST #%d Starts at vector=%d, test_inst_set", test_num, vector);
 
    repeat(1) @(posedge mstr_test_clk);
 
    repeat(1) @(posedge mstr_test_clk);
 
 
 
 
 
    activate_thread_sw(1);
 
    activate_thread_sw(1);
 
    wait_irq_set(1);
 
    wait_irq_set(1);
 
    host.wb_write(1, XGATE_XGIF_0, 16'h0002, WORD);
 
    host.wb_write(1, XGATE_XGIF_0, 16'h0002, WORD);
Line 753... Line 771... 
////////////////////////////////////////////////////////////////////////////////
 
////////////////////////////////////////////////////////////////////////////////
 
// check register bits - reset, read/write
 
// check register bits - reset, read/write
 
task reg_test_16;
 
task reg_test_16;
 
  begin
 
  begin
 
      test_num = test_num + 1;
 
      test_num = test_num + 1;
 
      $display("TEST #%d Starts at vector=%d, reg_test_16", test_num, vector);
 
    $display("\nTEST #%d Starts at vector=%d, reg_test_16", test_num, vector);
 
 
 
 
 
      system_reset;
 
      system_reset;
 
 
 
 
 
      host.wb_cmp(0, XGATE_XGMCTL,   16'h0000, WORD);    // verify reset
 
      host.wb_cmp(0, XGATE_XGMCTL,   16'h0000, WORD);    // verify reset
 
      host.wb_cmp(0, XGATE_XGCHID,   16'h0000, WORD);    // verify reset
 
      host.wb_cmp(0, XGATE_XGCHID,   16'h0000, WORD);    // verify reset
Line 954... Line 972... 
////////////////////////////////////////////////////////////////////////////////
 
////////////////////////////////////////////////////////////////////////////////
 
// check RAM Read/Write from host
 
// check RAM Read/Write from host
 
task host_ram;
 
task host_ram;
 
  begin
 
  begin
 
    test_num = test_num + 1;
 
    test_num = test_num + 1;
 
    $display("TEST #%d Starts at vector=%d, host_ram", test_num, vector);
 
    $display("\nTEST #%d Starts at vector=%d, host_ram", test_num, vector);
 
 
 
 
 
    host.wb_write(1, SYS_RAM_BASE, 16'h5555, WORD);
 
    host.wb_write(1, SYS_RAM_BASE, 16'h5555, WORD);
 
    host.wb_cmp(  0, SYS_RAM_BASE, 16'h5555, WORD);
 
    host.wb_cmp(  0, SYS_RAM_BASE, 16'h5555, WORD);
 
 
 
 
 
    repeat(5) @(posedge mstr_test_clk);
 
    repeat(5) @(posedge mstr_test_clk);
Line 1144... Line 1162... 
                          parameter ram_base = 0,
 
                          parameter ram_base = 0,
 
                          parameter ram_size = 16'hffff,
 
                          parameter ram_size = 16'hffff,
 
                          parameter slv1_base = 0,
 
                          parameter slv1_base = 0,
 
                          parameter slv1_size = 1,
 
                          parameter slv1_size = 1,
 
                          parameter slv2_base = 0,
 
                          parameter slv2_base = 0,
 
                          parameter slv2_size = 1)
 
                          parameter slv2_size = 1,
 
 
 
                          parameter ram_wait_states = 0) // Number between 0 and 15
 
  (
 
  (
 
  // System bus I/O
 
  // System bus I/O
 
  output reg                 sys_cyc,
 
  output reg                 sys_cyc,
 
  output reg                 sys_stb,
 
  output reg                 sys_stb,
 
  output reg                 sys_we,
 
  output reg                 sys_we,
Line 1203... Line 1222... 
  parameter [1:0] BUS_IDLE = 2'b00,
 
  parameter [1:0] BUS_IDLE = 2'b00,
 
                  HOST_OWNS = 2'b10,
 
                  HOST_OWNS = 2'b10,
 
                  RISC_OWNS = 2'b11;
 
                  RISC_OWNS = 2'b11;
 
 
 
 
 
  parameter max_bus_hold = 5;    // Max number of cycles any bus master can hold the system bus
 
  parameter max_bus_hold = 5;    // Max number of cycles any bus master can hold the system bus
 
  parameter ram_wait_states = 0; // Number between 0 and 15
 
 
 
  //////////////////////////////////////////////////////////////////////////////
 
  //////////////////////////////////////////////////////////////////////////////
 
  //
 
  //
 
  // Local Wires and Registers
 
  // Local Wires and Registers
 
  //
 
  //
 
  wire       ram_ack;        //
 
  wire       ram_ack;        //
Line 1382... Line 1400... 
  input               wb_cyc_i,     // valid bus cycle input
 
  input               wb_cyc_i,     // valid bus cycle input
 
  input         [1:0] wb_sel_i,      // Select byte in word bus transaction
 
  input         [1:0] wb_sel_i,      // Select byte in word bus transaction
 
  // Slave unique IO Signals
 
  // Slave unique IO Signals
 
  output reg          error_pulse,  // Error detected output pulse
 
  output reg          error_pulse,  // Error detected output pulse
 
  output reg          ack_pulse,    // Thread ack output pulse
 
  output reg          ack_pulse,    // Thread ack output pulse
 
 
 
  output              brk_pt,       // Break point
 
 
 
  input        [16:0] x_address,    // XGATE WISHBONE Master bus address
 
  input        [19:0] vector
 
  input        [19:0] vector
 
  );
 
  );
 
 
 
 
 
  wire                  async_rst_b;   // Asyncronous reset
 
  wire                  async_rst_b;   // Asyncronous reset
 
  wire                  sync_reset;    // Syncronous reset
 
  wire                  sync_reset;    // Syncronous reset
Line 1398... Line 1418... 
 
 
 
 
  reg  [15:0] check_point_reg;
 
  reg  [15:0] check_point_reg;
 
  reg  [15:0] channel_ack_reg;
 
  reg  [15:0] channel_ack_reg;
 
  reg  [15:0] channel_err_reg;
 
  reg  [15:0] channel_err_reg;
 
 
 
 
 
 
 
  reg  [15:0] brkpt_addr_reg;         // Break Point Address reg
 
 
 
  reg  [15:0] brkpt_cntl_reg;         // Break Point Control reg
 
 
 
 
 
  event check_point_wrt;
 
  event check_point_wrt;
 
  event channel_ack_wrt;
 
  event channel_ack_wrt;
 
  event channel_err_wrt;
 
  event channel_err_wrt;
 
 
 
 
 
  // Wires
 
  // Wires
Line 1442... Line 1465... 
  always @*
 
  always @*
 
    case (wb_adr_i) // synopsys parallel_case
 
    case (wb_adr_i) // synopsys parallel_case
 
      3'b000: rd_data_mux = check_point_reg;
 
      3'b000: rd_data_mux = check_point_reg;
 
      3'b001: rd_data_mux = channel_ack_reg;
 
      3'b001: rd_data_mux = channel_ack_reg;
 
      3'b010: rd_data_mux = channel_err_reg;
 
      3'b010: rd_data_mux = channel_err_reg;
 
      3'b011: rd_data_mux = 16'b0;
 
      3'b011: rd_data_mux = brkpt_cntl_reg;
 
 
 
      3'b100: rd_data_mux = brkpt_addr_reg;
 
 
 
      default: rd_data_mux = 16'b0;
 
    endcase
 
    endcase
 
 
 
 
 
  // generate wishbone write register strobes
 
  // generate wishbone write register strobes
 
  always @(posedge wb_clk_i or negedge arst_i)
 
  always @(posedge wb_clk_i or negedge arst_i)
 
    begin
 
    begin
Line 1480... Line 1505... 
               error_pulse <= 1'b1;
 
               error_pulse <= 1'b1;
 
               -> channel_err_wrt;
 
               -> channel_err_wrt;
 
             end
 
             end
 
           3'b011 :
 
           3'b011 :
 
             begin
 
             begin
 
 
 
               brkpt_cntl_reg[ 7:0] <= wb_sel_i[0] ? wb_dat_i[ 7:0] : brkpt_cntl_reg[ 7:0];
 
 
 
               brkpt_cntl_reg[15:8] <= wb_sel_i[1] ? wb_dat_i[15:8] : brkpt_cntl_reg[15:8];
 
 
 
             end
 
 
 
           3'b100 :
 
 
 
             begin
 
 
 
               brkpt_addr_reg[ 7:0] <= wb_sel_i[0] ? wb_dat_i[ 7:0] : brkpt_addr_reg[ 7:0];
 
 
 
               brkpt_addr_reg[15:8] <= wb_sel_i[1] ? wb_dat_i[15:8] : brkpt_addr_reg[15:8];
 
             end
 
             end
 
           default: ;
 
           default: ;
 
        endcase
 
        endcase
 
      else
 
      else
 
        begin
 
        begin

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