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[/] [xgate/] [trunk/] [bench/] [verilog/] [tst_bench_top.v] - Diff between revs 65 and 68

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Rev 65 Rev 68
Line 100... Line 100... 
  parameter XGMCTL_XGIE     = 15'h0001;
 
  parameter XGMCTL_XGIE     = 15'h0001;
 
 
 
 
 
  parameter CHECK_POINT = 16'h8000;
 
  parameter CHECK_POINT = 16'h8000;
 
  parameter CHANNEL_ACK = CHECK_POINT + 2;
 
  parameter CHANNEL_ACK = CHECK_POINT + 2;
 
  parameter CHANNEL_ERR = CHECK_POINT + 4;
 
  parameter CHANNEL_ERR = CHECK_POINT + 4;
 
 
 
  parameter TB_SEMPHORE     = CHECK_POINT + 10;
 
 
 
  parameter CHANNEL_XGIRQ_0 = CHECK_POINT + 16;
 
 
 
  parameter CHANNEL_XGIRQ_1 = CHECK_POINT + 18;
 
 
 
  parameter CHANNEL_XGIRQ_2 = CHECK_POINT + 20;
 
 
 
  parameter CHANNEL_XGIRQ_3 = CHECK_POINT + 22;
 
 
 
  parameter CHANNEL_XGIRQ_4 = CHECK_POINT + 24;
 
 
 
  parameter CHANNEL_XGIRQ_5 = CHECK_POINT + 26;
 
 
 
  parameter CHANNEL_XGIRQ_6 = CHECK_POINT + 28;
 
 
 
  parameter CHANNEL_XGIRQ_7 = CHECK_POINT + 30;
 
 
 
 
 
  parameter SYS_RAM_BASE = 24'h00_0000;
 
  parameter SYS_RAM_BASE = 24'h00_0000;
 
 
 
 
 
  parameter RAM_WAIT_STATES = 0; // Number between 0 and 15
 
  parameter RAM_WAIT_STATES = 1; // Number between 0 and 15
 
  parameter SYS_READ_DELAY = 10;
 
  parameter SYS_READ_DELAY = 10;
 
  parameter XGATE_ACCESS_DELAY = SYS_READ_DELAY + RAM_WAIT_STATES;
 
  parameter XGATE_ACCESS_DELAY = SYS_READ_DELAY + RAM_WAIT_STATES;
 
  parameter XGATE_SS_DELAY = XGATE_ACCESS_DELAY + RAM_WAIT_STATES;
 
  parameter XGATE_SS_DELAY = XGATE_ACCESS_DELAY + RAM_WAIT_STATES;
 
 
 
 
 
 
 
  parameter IRQ_BASE       = XGATE_BASE + 64;
 
 
 
  parameter IRQ_BYPS_0     = IRQ_BASE + 0;
 
 
 
  parameter IRQ_BYPS_1     = IRQ_BASE + 2;
 
 
 
  parameter IRQ_BYPS_2     = IRQ_BASE + 4;
 
 
 
  parameter IRQ_BYPS_3     = IRQ_BASE + 6;
 
 
 
  parameter IRQ_BYPS_4     = IRQ_BASE + 8;
 
 
 
  parameter IRQ_BYPS_5     = IRQ_BASE + 10;
 
 
 
  parameter IRQ_BYPS_6     = IRQ_BASE + 12;
 
 
 
  parameter IRQ_BYPS_7     = IRQ_BASE + 14;
 
 
 
 
 
  //
 
  //
 
  // wires && regs
 
  // wires && regs
 
  //
 
  //
 
  reg         mstr_test_clk;
 
  reg         mstr_test_clk;
Line 141... Line 159... 
 
 
 
 
  wire [15:0] tb_ram_out;
 
  wire [15:0] tb_ram_out;
 
 
 
 
 
  wire [15:0] tb_slave_dout; // WISHBONE data bus output from testbench slave module
 
  wire [15:0] tb_slave_dout; // WISHBONE data bus output from testbench slave module
 
  wire        error_pulse;   // Error detected output pulse from the testbench slave module
 
  wire        error_pulse;   // Error detected output pulse from the testbench slave module
 
  wire        test_reg_ack;  // WISHBONE ack from testbench slave module
 
  wire        tb_slave_ack;  // WISHBONE ack from testbench slave module
 
  wire        ack_pulse;     // Thread ack output pulse from testbench slave module
 
  wire        ack_pulse;     // Thread ack output pulse from testbench slave module
 
 
 
 
 
  wire        wbm_cyc_o;
 
  wire        wbm_cyc_o;
 
  wire        wbm_stb_o;
 
  wire        wbm_stb_o;
 
  wire        wbm_we_o;
 
  wire        wbm_we_o;
Line 291... Line 309... 
  bus_arbitration  #(.dwidth(16),
 
  bus_arbitration  #(.dwidth(16),
 
                     .awidth(24),
 
                     .awidth(24),
 
                     .ram_base(0),
 
                     .ram_base(0),
 
                     .ram_size(17'h10000),
 
                     .ram_size(17'h10000),
 
                     .slv1_base(XGATE_BASE),
 
                     .slv1_base(XGATE_BASE),
 
                     .slv1_size(64),
 
                     .slv1_size(128),
 
                     .slv2_base(CHECK_POINT),
 
                     .slv2_base(CHECK_POINT),
 
                     .slv2_size(8),
 
                     .slv2_size(32),
 
                     .ram_wait_states(RAM_WAIT_STATES)
 
                     .ram_wait_states(RAM_WAIT_STATES)
 
)
 
)
 
    arb(
 
    arb(
 
    // System bus I/O
 
    // System bus I/O
 
    .sys_cyc( sys_cyc ),
 
    .sys_cyc( sys_cyc ),
Line 331... Line 349... 
    .slv1_stb( xgate_s_stb ),
 
    .slv1_stb( xgate_s_stb ),
 
    .slv1_ack( xgate_s_ack ),
 
    .slv1_ack( xgate_s_ack ),
 
    .slv1_din( xgate_s_dout ),
 
    .slv1_din( xgate_s_dout ),
 
    // Slave #2 Bus I/O
 
    // Slave #2 Bus I/O
 
    .slv2_stb( slv2_stb ),
 
    .slv2_stb( slv2_stb ),
 
    .slv2_ack( test_reg_ack ),
 
    .slv2_ack( tb_slave_ack ),
 
    .slv2_din( tb_slave_dout ),
 
    .slv2_din( tb_slave_dout ),
 
    // Miscellaneous
 
    // Miscellaneous
 
    .host_clk( mstr_test_clk ),
 
    .host_clk( mstr_test_clk ),
 
    .risc_clk( mstr_test_clk ),
 
    .risc_clk( mstr_test_clk ),
 
    .rst( rstn ),  // No Connect
 
    .rst( rstn ),  // No Connect
Line 343... Line 361... 
    .rty( 1'b0 )   // No Connect
 
    .rty( 1'b0 )   // No Connect
 
  );
 
  );
 
 
 
 
 
  // hookup XGATE core - Parameters take all default values
 
  // hookup XGATE core - Parameters take all default values
 
  xgate_top  #(.SINGLE_CYCLE(1'b0),
 
  xgate_top  #(.SINGLE_CYCLE(1'b0),
 
 
 
               .WB_RD_DEFAULT(1'b0),
 
               .MAX_CHANNEL(MAX_CHANNEL))    // Max XGATE Interrupt Channel Number
 
               .MAX_CHANNEL(MAX_CHANNEL))    // Max XGATE Interrupt Channel Number
 
          xgate(
 
          xgate(
 
          // Wishbone slave interface
 
          // Wishbone slave interface
 
          .wbs_clk_i( mstr_test_clk ),
 
          .wbs_clk_i( mstr_test_clk ),
 
          .wbs_rst_i( 1'b0 ),         // sync_reset
 
          .wbs_rst_i( 1'b0 ),         // sync_reset
 
          .arst_i( rstn ),            // async resetn
 
          .arst_i( rstn ),            // async resetn
 
          .wbs_adr_i( sys_adr[5:1] ),
 
          .wbs_adr_i( sys_adr[6:1] ),
 
          .wbs_dat_i( sys_dout ),
 
          .wbs_dat_i( sys_dout ),
 
          .wbs_dat_o( xgate_s_dout ),
 
          .wbs_dat_o( xgate_s_dout ),
 
          .wbs_we_i( sys_we ),
 
          .wbs_we_i( sys_we ),
 
          .wbs_stb_i( xgate_s_stb ),
 
          .wbs_stb_i( xgate_s_stb ),
 
          .wbs_cyc_i( sys_cyc ),
 
          .wbs_cyc_i( sys_cyc ),
Line 380... Line 399... 
          .secure_mode_i( 1'b0 ),
 
          .secure_mode_i( 1'b0 ),
 
          .scantestmode( scantestmode )
 
          .scantestmode( scantestmode )
 
  );
 
  );
 
 
 
 
 
  tb_slave #(.DWIDTH(16),
 
  tb_slave #(.DWIDTH(16),
 
             .SINGLE_CYCLE(1'b1))
 
             .SINGLE_CYCLE(1'b1),
 
 
 
             .MAX_CHANNEL(MAX_CHANNEL))
 
          tb_slave_regs(
 
          tb_slave_regs(
 
          // wishbone interface
 
          // wishbone interface
 
          .wb_clk_i( mstr_test_clk ),
 
          .wb_clk_i( mstr_test_clk ),
 
          .wb_rst_i( 1'b0 ),
 
          .wb_rst_i( 1'b0 ),
 
          .arst_i( rstn ),
 
          .arst_i( rstn ),
 
          .wb_adr_i( sys_adr[3:1] ),
 
          .wb_adr_i( sys_adr[4:1] ),
 
          .wb_dat_i( sys_dout ),
 
          .wb_dat_i( sys_dout ),
 
          .wb_dat_o( tb_slave_dout),
 
          .wb_dat_o( tb_slave_dout),
 
          .wb_we_i( sys_we ),
 
          .wb_we_i( sys_we ),
 
          .wb_stb_i( slv2_stb ),
 
          .wb_stb_i( slv2_stb ),
 
          .wb_cyc_i( sys_cyc ),
 
          .wb_cyc_i( sys_cyc ),
 
          .wb_sel_i( sys_sel ),
 
          .wb_sel_i( sys_sel ),
 
          .wb_ack_o( test_reg_ack ),
 
          .wb_ack_o( tb_slave_ack ),
 
 
 
 
 
          .ack_pulse( ack_pulse ),
 
          .ack_pulse( ack_pulse ),
 
          .error_pulse( error_pulse ),
 
          .error_pulse( error_pulse ),
 
          .brk_pt(  ),
 
          .brk_pt(  ),
 
          .x_address( wbm_adr_o ),
 
          .x_address( wbm_adr_o ),
 
 
 
          .xgif( xgif ),
 
          .vector( vector )
 
          .vector( vector )
 
  );
 
  );
 
 
 
 
 
 
 
 
 
 
 
 
Line 440... Line 461... 
 
 
 
 
    test_chid_debug;
 
    test_chid_debug;
 
 
 
 
 
    reg_test_16;
 
    reg_test_16;
 
 
 
 
 
 
 
    reg_irq;
 
 
 
 
 
    //host_ram;
 
    //host_ram;
 
 
 
 
 
    // End testing
 
    // End testing
 
    wrap_up;
 
    wrap_up;
 
  end
 
  end
Line 454... Line 477... 
  begin
 
  begin
 
    test_num = test_num + 1;
 
    test_num = test_num + 1;
 
    $display("\nTEST #%d Starts at vector=%d, test_chid_debug", test_num, vector);
 
    $display("\nTEST #%d Starts at vector=%d, test_chid_debug", test_num, vector);
 
    $readmemh("../../../bench/verilog/debug_test.v", p_ram.ram_8);
 
    $readmemh("../../../bench/verilog/debug_test.v", p_ram.ram_8);
 
 
 
 
 
 
 
    // Enable interrupts to RISC
 
 
 
    host.wb_write(0, IRQ_BYPS_0,  16'h0000, WORD);
 
 
 
 
 
    data_xgmctl = XGMCTL_XGBRKIEM | XGMCTL_XGBRKIE;
 
    data_xgmctl = XGMCTL_XGBRKIEM | XGMCTL_XGBRKIE;
 
    host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD);    // Enable interrupt on BRK instruction
 
    host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD);    // Enable interrupt on BRK instruction
 
    $display("BRK Software Error Interrupt enabled at vector=%d", vector);
 
    $display("BRK Software Error Interrupt enabled at vector=%d", vector);
 
 
 
 
 
    activate_thread_sw(3);
 
    activate_thread_sw(3);
Line 548... Line 574... 
  begin
 
  begin
 
    test_num = test_num + 1;
 
    test_num = test_num + 1;
 
    $display("\nTEST #%d Starts at vector=%d, test_debug_bit", test_num, vector);
 
    $display("\nTEST #%d Starts at vector=%d, test_debug_bit", test_num, vector);
 
    $readmemh("../../../bench/verilog/debug_test.v", p_ram.ram_8);
 
    $readmemh("../../../bench/verilog/debug_test.v", p_ram.ram_8);
 
 
 
 
 
 
 
    // Enable interrupts to RISC
 
 
 
    host.wb_write(0, IRQ_BYPS_0,  16'h0000, WORD);
 
 
 
 
 
    data_xgmctl = XGMCTL_XGBRKIEM | XGMCTL_XGBRKIE;
 
    data_xgmctl = XGMCTL_XGBRKIEM | XGMCTL_XGBRKIE;
 
    host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD);    // Enable interrupt on BRK instruction
 
    host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD);    // Enable interrupt on BRK instruction
 
 
 
 
 
    activate_thread_sw(2);
 
    activate_thread_sw(2);
 
 
 
 
Line 612... Line 641... 
  begin
 
  begin
 
    test_num = test_num + 1;
 
    test_num = test_num + 1;
 
    $display("\nTEST #%d Starts at vector=%d, test_debug_mode", test_num, vector);
 
    $display("\nTEST #%d Starts at vector=%d, test_debug_mode", test_num, vector);
 
    $readmemh("../../../bench/verilog/debug_test.v", p_ram.ram_8);
 
    $readmemh("../../../bench/verilog/debug_test.v", p_ram.ram_8);
 
 
 
 
 
 
 
    // Enable interrupts to RISC
 
 
 
    host.wb_write(0, IRQ_BYPS_0,  16'h0000, WORD);
 
 
 
 
 
    data_xgmctl = XGMCTL_XGBRKIEM | XGMCTL_XGBRKIE;
 
    data_xgmctl = XGMCTL_XGBRKIEM | XGMCTL_XGBRKIE;
 
    host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD);    // Enable interrupt on BRK instruction
 
    host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD);    // Enable interrupt on BRK instruction
 
 
 
 
 
    activate_thread_sw(1);
 
    activate_thread_sw(1);
 
 
 
 
Line 694... Line 726... 
    $readmemh("../../../bench/verilog/inst_test.v", p_ram.ram_8);
 
    $readmemh("../../../bench/verilog/inst_test.v", p_ram.ram_8);
 
    test_num = test_num + 1;
 
    test_num = test_num + 1;
 
    $display("\nTEST #%d Starts at vector=%d, test_inst_set", test_num, vector);
 
    $display("\nTEST #%d Starts at vector=%d, test_inst_set", test_num, vector);
 
    repeat(1) @(posedge mstr_test_clk);
 
    repeat(1) @(posedge mstr_test_clk);
 
 
 
 
 
 
 
    // Enable interrupts to RISC
 
 
 
    host.wb_write(0, IRQ_BYPS_0,  16'h0000, WORD);
 
 
 
 
 
    activate_thread_sw(1);
 
    activate_thread_sw(1);
 
    wait_irq_set(1);
 
    wait_irq_set(1);
 
    host.wb_write(1, XGATE_XGIF_0, 16'h0002, WORD);
 
    host.wb_write(1, XGATE_XGIF_0, 16'h0002, WORD);
 
 
 
 
 
    activate_thread_sw(2);
 
    activate_thread_sw(2);
Line 966... Line 1001... 
    host.wb_cmp(0, XGATE_XGR7,    16'h6778, WORD);
 
    host.wb_cmp(0, XGATE_XGR7,    16'h6778, WORD);
 
 
 
 
 
  end
 
  end
 
endtask
 
endtask
 
 
 
 
 
 
 
////////////////////////////////////////////////////////////////////////////////
 
 
 
// check register bits - reset, read/write
 
 
 
task reg_irq;
 
 
 
  begin
 
 
 
    test_num = test_num + 1;
 
 
 
    $display("\nTEST #%d Starts at vector=%d, reg_irq", test_num, vector);
 
 
 
    $readmemh("../../../bench/verilog/irq_test.v", p_ram.ram_8);
 
 
 
 
 
 
 
    system_reset;
 
 
 
 
 
 
 
    host.wb_cmp(0, IRQ_BYPS_0,   16'hFFFF, WORD);        // verify reset
 
 
 
    host.wb_cmp(0, IRQ_BYPS_1,   16'hFFFF, WORD);        // verify reset
 
 
 
    host.wb_cmp(0, IRQ_BYPS_2,   16'hFFFF, WORD);        // verify reset
 
 
 
    host.wb_cmp(0, IRQ_BYPS_3,   16'hFFFF, WORD);        // verify reset
 
 
 
    host.wb_cmp(0, IRQ_BYPS_4,   16'hFFFF, WORD);        // verify reset
 
 
 
    host.wb_cmp(0, IRQ_BYPS_5,   16'hFFFF, WORD);        // verify reset
 
 
 
    host.wb_cmp(0, IRQ_BYPS_6,   16'hFFFF, WORD);        // verify reset
 
 
 
    host.wb_cmp(0, IRQ_BYPS_7,   16'hFFFF, WORD);        // verify reset
 
 
 
 
 
 
 
 
 
 
 
    // Test the Xgate IRQ Bypass Registers (IRQ_BYPS)
 
 
 
    host.wb_write(0, IRQ_BYPS_0,  16'hAAAA, WORD);
 
 
 
    host.wb_cmp(0, IRQ_BYPS_0,    16'hAAAA, WORD);
 
 
 
    host.wb_write(0, IRQ_BYPS_0,  16'h5555, WORD);
 
 
 
    host.wb_cmp(0, IRQ_BYPS_0,    16'h5555, WORD);
 
 
 
 
 
 
 
    host.wb_write(0, IRQ_BYPS_0,  16'hFF66, L_BYTE);
 
 
 
    host.wb_cmp(0, IRQ_BYPS_0,    16'h5566, WORD);
 
 
 
    host.wb_write(0, IRQ_BYPS_0,  16'h33FF, H_BYTE);
 
 
 
    host.wb_cmp(0, IRQ_BYPS_0,    16'h3366, WORD);
 
 
 
    host.wb_write(0, IRQ_BYPS_0,  16'hFFFF, H_BYTE);
 
 
 
 
 
 
 
    channel_req[17] = 1'b1; //
 
 
 
    repeat(4) @(posedge mstr_test_clk);
 
 
 
    host.wb_cmp(0, CHANNEL_XGIRQ_1,    16'h0002, WORD);
 
 
 
    channel_req[17] = 1'b0; //
 
 
 
    repeat(4) @(posedge mstr_test_clk);
 
 
 
    host.wb_cmp(0, CHANNEL_XGIRQ_1,    16'h0000, WORD);
 
 
 
 
 
 
 
    host.wb_write(0, TB_SEMPHORE,  16'h0000, WORD);
 
 
 
    host.wb_write(0, IRQ_BYPS_0,  16'h0000, WORD);
 
 
 
    host.wb_write(0, IRQ_BYPS_0,  16'h0000, WORD);
 
 
 
    data_xgmctl = XGMCTL_XGEM | XGMCTL_XGE;
 
 
 
    host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD);   // Enable XGATE
 
 
 
    repeat(XGATE_ACCESS_DELAY+2) @(posedge mstr_test_clk);
 
 
 
    channel_req[3:1] = 3'b111; //
 
 
 
 
 
 
 
    q = 0;
 
 
 
    // The Xgate test program is in an infinate loop for the test bench semaphore register to be changed
 
 
 
    while (q == 0)  // Look for change in test bench semapore register
 
 
 
      begin
 
 
 
        host.wb_read(1, TB_SEMPHORE, q, WORD);
 
 
 
      end
 
 
 
 
 
 
 
    if (q != 1)
 
 
 
      begin
 
 
 
        $display("IRQ test failure, Wrong interrupt being processed! Interrupt=%d, vector=%d", q, vector);
 
 
 
      end
 
 
 
 
 
 
 
    channel_req[1] = 1'b0; //
 
 
 
    repeat(XGATE_ACCESS_DELAY+2) @(posedge mstr_test_clk);
 
 
 
    host.wb_write(0, TB_SEMPHORE,  16'h0000, WORD);
 
 
 
    repeat(XGATE_ACCESS_DELAY+2) @(posedge mstr_test_clk);
 
 
 
 
 
 
 
//    host.wb_cmp(0, CHANNEL_XGIRQ_0, 16'h0002, WORD);  // Verify Xgate output interrupt flag set
 
 
 
//    host.wb_cmp(0, XGATE_XGIF_0,    16'h0002, WORD);  // Verify Xgate interrupt status bit set
 
 
 
    host.wb_write(1, XGATE_XGIF_0, 16'h0002, WORD);  // Clear Interrupt Flag from Xgate
 
 
 
//    host.wb_cmp(0, XGATE_XGIF_0,    16'h0000, WORD);  // Verify flag cleared
 
 
 
 
 
 
 
    q = 0;
 
 
 
    // The Xgate test program is in an infinate loop for the test bench semaphore register to be changed
 
 
 
    while (q == 0)  // Look for change in test bench semapore register
 
 
 
      begin
 
 
 
        host.wb_read(1, TB_SEMPHORE, q, WORD);
 
 
 
      end
 
 
 
 
 
 
 
    if (q != 2)
 
 
 
      begin
 
 
 
        $display("IRQ test failure, Wrong interrupt being processed! Interrupt=%d, vector=%d", q, vector);
 
 
 
      end
 
 
 
 
 
 
 
    channel_req[2] = 1'b0; //
 
 
 
    repeat(XGATE_ACCESS_DELAY+2) @(posedge mstr_test_clk);
 
 
 
    host.wb_write(0, TB_SEMPHORE,  16'h0000, WORD);
 
 
 
    repeat(XGATE_ACCESS_DELAY+2) @(posedge mstr_test_clk);
 
 
 
 
 
 
 
//    host.wb_cmp(0, CHANNEL_XGIRQ_0, 16'h0002, WORD);  // Verify Xgate output interrupt flag set
 
 
 
//    host.wb_cmp(0, XGATE_XGIF_0,    16'h0002, WORD);  // Verify Xgate interrupt status bit set
 
 
 
    host.wb_write(1, XGATE_XGIF_0, 16'h0004, WORD);  // Clear Interrupt Flag from Xgate
 
 
 
//    host.wb_cmp(0, XGATE_XGIF_0,    16'h0000, WORD);  // Verify flag cleared
 
 
 
 
 
 
 
    q = 0;
 
 
 
    // The Xgate test program is in an infinate loop for the test bench semaphore register to be changed
 
 
 
    while (q == 0)  // Look for change in test bench semapore register
 
 
 
      begin
 
 
 
        host.wb_read(1, TB_SEMPHORE, q, WORD);
 
 
 
      end
 
 
 
 
 
 
 
    if (q != 3)
 
 
 
      begin
 
 
 
        $display("IRQ test failure, Wrong interrupt being processed! Interrupt=%d, vector=%d", q, vector);
 
 
 
      end
 
 
 
 
 
 
 
    channel_req[3] = 1'b0; //
 
 
 
    repeat(XGATE_ACCESS_DELAY+2) @(posedge mstr_test_clk);
 
 
 
    host.wb_write(0, TB_SEMPHORE,  16'h0000, WORD);
 
 
 
    repeat(XGATE_ACCESS_DELAY+2) @(posedge mstr_test_clk);
 
 
 
 
 
 
 
//    host.wb_cmp(0, CHANNEL_XGIRQ_0, 16'h0002, WORD);  // Verify Xgate output interrupt flag set
 
 
 
//    host.wb_cmp(0, XGATE_XGIF_0,    16'h0002, WORD);  // Verify Xgate interrupt status bit set
 
 
 
    host.wb_write(1, XGATE_XGIF_0, 16'h0008, WORD);  // Clear Interrupt Flag from Xgate
 
 
 
//    host.wb_cmp(0, XGATE_XGIF_0,    16'h0000, WORD);  // Verify flag cleared
 
 
 
 
 
 
 
  end
 
 
 
endtask
 
 
 
 
 
 
 
 
 
////////////////////////////////////////////////////////////////////////////////
 
////////////////////////////////////////////////////////////////////////////////
 
// check RAM Read/Write from host
 
// check RAM Read/Write from host
 
task host_ram;
 
task host_ram;
 
  begin
 
  begin
Line 1332... Line 1483... 
  assign ram_ack_dly = (ack_dly_cnt == ram_wait_states);
 
  assign ram_ack_dly = (ack_dly_cnt == ram_wait_states);
 
  assign ram_ack = ram_sel && ram_ack_dly;
 
  assign ram_ack = ram_sel && ram_ack_dly;
 
 
 
 
 
 
 
 
 
  // Create the System Read Data Bus from the Slave output data buses
 
  // Create the System Read Data Bus from the Slave output data buses
 
  assign sys_din = ({dwidth{slv1_stb}} & slv1_din) |
 
  assign sys_din = ({dwidth{1'b1}} & slv1_din) |
 
                   ({dwidth{slv2_stb}} & slv2_din) |
 
                   ({dwidth{slv2_stb}} & slv2_din) |
 
                   ({dwidth{ram_sel}}  & ram_dout);
 
                   ({dwidth{ram_sel}}  & ram_dout);
 
 
 
 
 
  // Mux for System Bus access
 
  // Mux for System Bus access
 
  always @*
 
  always @*
Line 1383... Line 1534... 
 
 
 
 
////////////////////////////////////////////////////////////////////////////////
 
////////////////////////////////////////////////////////////////////////////////
 
////////////////////////////////////////////////////////////////////////////////
 
////////////////////////////////////////////////////////////////////////////////
 
////////////////////////////////////////////////////////////////////////////////
 
////////////////////////////////////////////////////////////////////////////////
 
module tb_slave #(parameter SINGLE_CYCLE = 1'b0,  // No bus wait state added
 
module tb_slave #(parameter SINGLE_CYCLE = 1'b0,  // No bus wait state added
 
 
 
                  parameter MAX_CHANNEL = 127,    // Max XGATE Interrupt Channel Number
 
                  parameter DWIDTH = 16)          // Data bus width
 
                  parameter DWIDTH = 16)          // Data bus width
 
  (
 
  (
 
  // Wishbone Signals
 
  // Wishbone Signals
 
  output [DWIDTH-1:0] wb_dat_o,      // databus output
 
  output [DWIDTH-1:0] wb_dat_o,      // databus output
 
  output              wb_ack_o,     // bus cycle acknowledge output
 
  output              wb_ack_o,     // bus cycle acknowledge output
 
  input               wb_clk_i,     // master clock input
 
  input               wb_clk_i,     // master clock input
 
  input               wb_rst_i,     // synchronous active high reset
 
  input               wb_rst_i,     // synchronous active high reset
 
  input               arst_i,       // asynchronous reset
 
  input               arst_i,       // asynchronous reset
 
  input         [2:0] wb_adr_i,      // lower address bits
 
  input         [3:0] wb_adr_i,      // lower address bits
 
  input  [DWIDTH-1:0] wb_dat_i,      // databus input
 
  input  [DWIDTH-1:0] wb_dat_i,      // databus input
 
  input               wb_we_i,      // write enable input
 
  input               wb_we_i,      // write enable input
 
  input               wb_stb_i,     // stobe/core select signal
 
  input               wb_stb_i,     // stobe/core select signal
 
  input               wb_cyc_i,     // valid bus cycle input
 
  input               wb_cyc_i,     // valid bus cycle input
 
  input         [1:0] wb_sel_i,      // Select byte in word bus transaction
 
  input         [1:0] wb_sel_i,      // Select byte in word bus transaction
 
  // Slave unique IO Signals
 
  // Slave unique IO Signals
 
  output reg          error_pulse,  // Error detected output pulse
 
  output reg          error_pulse,  // Error detected output pulse
 
  output reg          ack_pulse,    // Thread ack output pulse
 
  output reg          ack_pulse,    // Thread ack output pulse
 
  output              brk_pt,       // Break point
 
  output              brk_pt,       // Break point
 
  input        [16:0] x_address,    // XGATE WISHBONE Master bus address
 
  input        [15:0] x_address,    // XGATE WISHBONE Master bus address
 
 
 
  input [MAX_CHANNEL:0] xgif,       // XGATE Interrupt Flag to Host
 
  input        [19:0] vector
 
  input        [19:0] vector
 
  );
 
  );
 
 
 
 
 
  wire                  async_rst_b;   // Asyncronous reset
 
  wire                  async_rst_b;   // Asyncronous reset
 
  wire                  sync_reset;    // Syncronous reset
 
  wire                  sync_reset;    // Syncronous reset
Line 1414... Line 1567... 
  // registers
 
  // registers
 
  reg                bus_wait_state;  // Holdoff wb_ack_o for one clock to add wait state
 
  reg                bus_wait_state;  // Holdoff wb_ack_o for one clock to add wait state
 
  reg  [DWIDTH-1:0]  rd_data_mux;     // Pseudo Register, WISHBONE Read Data Mux
 
  reg  [DWIDTH-1:0]  rd_data_mux;     // Pseudo Register, WISHBONE Read Data Mux
 
  reg  [DWIDTH-1:0]  rd_data_reg;     // Latch for WISHBONE Read Data
 
  reg  [DWIDTH-1:0]  rd_data_reg;     // Latch for WISHBONE Read Data
 
 
 
 
 
  reg  [15:0] check_point_reg;
 
  reg  [DWIDTH-1:0] check_point_reg;
 
  reg  [15:0] channel_ack_reg;
 
  reg  [DWIDTH-1:0] channel_ack_reg;
 
  reg  [15:0] channel_err_reg;
 
  reg  [DWIDTH-1:0] channel_err_reg;
 
 
 
 
 
  reg  [15:0] brkpt_addr_reg;         // Break Point Address reg
 
  reg  [DWIDTH-1:0] brkpt_addr_reg;  // Break Point Address reg
 
  reg  [15:0] brkpt_cntl_reg;         // Break Point Control reg
 
  reg  [DWIDTH-1:0] brkpt_cntl_reg;  // Break Point Control reg
 
 
 
 
 
 
 
  reg  [DWIDTH-1:0] tb_semaphr_reg;  // Test bench semaphore reg
 
 
 
 
 
  event check_point_wrt;
 
  event check_point_wrt;
 
  event channel_ack_wrt;
 
  event channel_ack_wrt;
 
  event channel_err_wrt;
 
  event channel_err_wrt;
 
 
 
 
Line 1462... Line 1617... 
      rd_data_reg <= rd_data_mux;
 
      rd_data_reg <= rd_data_mux;
 
 
 
 
 
  // WISHBONE Read Data Mux
 
  // WISHBONE Read Data Mux
 
  always @*
 
  always @*
 
    case (wb_adr_i) // synopsys parallel_case
 
    case (wb_adr_i) // synopsys parallel_case
 
      3'b000: rd_data_mux = check_point_reg;
 
      4'b0000: rd_data_mux = check_point_reg;
 
      3'b001: rd_data_mux = channel_ack_reg;
 
      4'b0001: rd_data_mux = channel_ack_reg;
 
      3'b010: rd_data_mux = channel_err_reg;
 
      4'b0010: rd_data_mux = channel_err_reg;
 
      3'b011: rd_data_mux = brkpt_cntl_reg;
 
      4'b0011: rd_data_mux = brkpt_cntl_reg;
 
      3'b100: rd_data_mux = brkpt_addr_reg;
 
      4'b0100: rd_data_mux = brkpt_addr_reg;
 
      default: rd_data_mux = 16'b0;
 
      4'b0101: rd_data_mux = tb_semaphr_reg;
 
 
 
      4'b1000: rd_data_mux = xgif[15: 0];
 
 
 
      4'b1001: rd_data_mux = xgif[31:16];
 
 
 
      4'b1010: rd_data_mux = xgif[47:32];
 
 
 
      4'b1011: rd_data_mux = xgif[63:48];
 
 
 
      4'b1100: rd_data_mux = xgif[79:64];
 
 
 
      4'b1101: rd_data_mux = xgif[95:80];
 
 
 
      4'b1110: rd_data_mux = xgif[111:96];
 
 
 
      4'b1111: rd_data_mux = xgif[127:112];
 
 
 
      default: rd_data_mux = {DWIDTH{1'b0}};
 
    endcase
 
    endcase
 
 
 
 
 
  // generate wishbone write register strobes
 
  // generate wishbone write register strobes
 
  always @(posedge wb_clk_i or negedge arst_i)
 
  always @(posedge wb_clk_i or negedge arst_i)
 
    begin
 
    begin
Line 1480... Line 1644... 
          check_point_reg <= 0;
 
          check_point_reg <= 0;
 
          channel_ack_reg <= 0;
 
          channel_ack_reg <= 0;
 
          channel_err_reg <= 0;
 
          channel_err_reg <= 0;
 
          ack_pulse       <= 0;
 
          ack_pulse       <= 0;
 
          error_pulse     <= 0;
 
          error_pulse     <= 0;
 
 
 
          brkpt_cntl_reg  <= 0;
 
 
 
          brkpt_addr_reg  <= 0;
 
 
 
          tb_semaphr_reg  <= 0;
 
        end
 
        end
 
      else if (wb_wacc)
 
      else if (wb_wacc)
 
        case (wb_adr_i) // synopsys parallel_case
 
        case (wb_adr_i) // synopsys parallel_case
 
           3'b000 :
 
           3'b000 :
 
             begin
 
             begin
Line 1513... Line 1680... 
           3'b100 :
 
           3'b100 :
 
             begin
 
             begin
 
               brkpt_addr_reg[ 7:0] <= wb_sel_i[0] ? wb_dat_i[ 7:0] : brkpt_addr_reg[ 7:0];
 
               brkpt_addr_reg[ 7:0] <= wb_sel_i[0] ? wb_dat_i[ 7:0] : brkpt_addr_reg[ 7:0];
 
               brkpt_addr_reg[15:8] <= wb_sel_i[1] ? wb_dat_i[15:8] : brkpt_addr_reg[15:8];
 
               brkpt_addr_reg[15:8] <= wb_sel_i[1] ? wb_dat_i[15:8] : brkpt_addr_reg[15:8];
 
             end
 
             end
 
 
 
           3'b101 :
 
 
 
             begin
 
 
 
               tb_semaphr_reg[ 7:0] <= wb_sel_i[0] ? wb_dat_i[ 7:0] : tb_semaphr_reg[ 7:0];
 
 
 
               tb_semaphr_reg[15:8] <= wb_sel_i[1] ? wb_dat_i[15:8] : tb_semaphr_reg[15:8];
 
 
 
             end
 
           default: ;
 
           default: ;
 
        endcase
 
        endcase
 
      else
 
      else
 
        begin
 
        begin
 
          ack_pulse   <= 0;
 
          ack_pulse   <= 0;

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