| Line 142... |
Line 142... |
reg rstn;
|
reg rstn;
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reg sync_reset;
|
reg sync_reset;
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reg por_reset_b;
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reg por_reset_b;
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reg scantestmode;
|
reg scantestmode;
|
|
|
reg [MAX_CHANNEL:0] channel_req; // XGATE Interrupt inputs
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reg [MAX_CHANNEL:1] channel_req; // XGATE Interrupt inputs
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wire [MAX_CHANNEL:0] xgif; // XGATE Interrupt outputs
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wire [MAX_CHANNEL:1] xgif; // XGATE Interrupt outputs
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wire [ 7:0] xgswt; // XGATE Software Trigger outputs
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wire [ 7:0] xgswt; // XGATE Software Trigger outputs
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wire xg_sw_irq; // Xgate Software Error interrupt
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wire xg_sw_irq; // Xgate Software Error interrupt
|
|
|
|
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wire [15:0] wbm_dat_o; // WISHBONE Master Mode data output from XGATE
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wire [15:0] wbm_dat_o; // WISHBONE Master Mode data output from XGATE
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| Line 392... |
Line 392... |
|
|
.xgif( xgif ), // XGATE Interrupt Flag output
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.xgif( xgif ), // XGATE Interrupt Flag output
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.xg_sw_irq( xg_sw_irq ), // XGATE Software Error Interrupt Flag output
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.xg_sw_irq( xg_sw_irq ), // XGATE Software Error Interrupt Flag output
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.xgswt( xgswt ),
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.xgswt( xgswt ),
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.risc_clk( mstr_test_clk ),
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.risc_clk( mstr_test_clk ),
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.chan_req_i( {channel_req[MAX_CHANNEL:40], xgswt, channel_req[31:0]} ),
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.chan_req_i( {channel_req[MAX_CHANNEL:40], xgswt, channel_req[31:1]} ),
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.debug_mode_i( 1'b0 ),
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.debug_mode_i( 1'b0 ),
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.secure_mode_i( 1'b0 ),
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.secure_mode_i( 1'b0 ),
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.scantestmode( scantestmode )
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.scantestmode( scantestmode )
|
);
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);
|
|
|
| Line 822... |
Line 822... |
host.wb_cmp(0, XGATE_XGIF_5, 16'h0000, WORD); // verify reset
|
host.wb_cmp(0, XGATE_XGIF_5, 16'h0000, WORD); // verify reset
|
host.wb_cmp(0, XGATE_XGIF_4, 16'h0000, WORD); // verify reset
|
host.wb_cmp(0, XGATE_XGIF_4, 16'h0000, WORD); // verify reset
|
host.wb_cmp(0, XGATE_XGIF_3, 16'h0000, WORD); // verify reset
|
host.wb_cmp(0, XGATE_XGIF_3, 16'h0000, WORD); // verify reset
|
host.wb_cmp(0, XGATE_XGIF_2, 16'h0000, WORD); // verify reset
|
host.wb_cmp(0, XGATE_XGIF_2, 16'h0000, WORD); // verify reset
|
host.wb_cmp(0, XGATE_XGIF_1, 16'h0000, WORD); // verify reset
|
host.wb_cmp(0, XGATE_XGIF_1, 16'h0000, WORD); // verify reset
|
host.wb_cmp(0, XGATE_XGIF_0, 16'h0001, WORD); // verify reset
|
host.wb_cmp(0, XGATE_XGIF_0, 16'h0000, WORD); // verify reset
|
host.wb_cmp(0, XGATE_XGSWT, 16'h0000, WORD); // verify reset
|
host.wb_cmp(0, XGATE_XGSWT, 16'h0000, WORD); // verify reset
|
host.wb_cmp(0, XGATE_XGSEM, 16'h0000, WORD); // verify reset
|
host.wb_cmp(0, XGATE_XGSEM, 16'h0000, WORD); // verify reset
|
host.wb_cmp(0, XGATE_XGCCR, 16'h0000, WORD); // verify reset
|
host.wb_cmp(0, XGATE_XGCCR, 16'h0000, WORD); // verify reset
|
host.wb_cmp(0, XGATE_XGPC, 16'h0000, WORD); // verify reset
|
host.wb_cmp(0, XGATE_XGPC, 16'h0000, WORD); // verify reset
|
host.wb_cmp(0, XGATE_XGR1, 16'h0000, WORD); // verify reset
|
host.wb_cmp(0, XGATE_XGR1, 16'h0000, WORD); // verify reset
|
| Line 1002... |
Line 1002... |
|
|
end
|
end
|
endtask
|
endtask
|
|
|
////////////////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////////////////
|
// check register bits - reset, read/write
|
// check irq register bits - reset, read/write
|
task reg_irq;
|
task reg_irq;
|
begin
|
begin
|
test_num = test_num + 1;
|
test_num = test_num + 1;
|
$display("\nTEST #%d Starts at vector=%d, reg_irq", test_num, vector);
|
$display("\nTEST #%d Starts at vector=%d, reg_irq", test_num, vector);
|
$readmemh("../../../bench/verilog/irq_test.v", p_ram.ram_8);
|
$readmemh("../../../bench/verilog/irq_test.v", p_ram.ram_8);
|
|
|
system_reset;
|
system_reset;
|
|
|
host.wb_cmp(0, IRQ_BYPS_0, 16'hFFFF, WORD); // verify reset
|
host.wb_cmp(0, IRQ_BYPS_0, 16'hFFFE, WORD); // verify reset
|
host.wb_cmp(0, IRQ_BYPS_1, 16'hFFFF, WORD); // verify reset
|
host.wb_cmp(0, IRQ_BYPS_1, 16'hFFFF, WORD); // verify reset
|
host.wb_cmp(0, IRQ_BYPS_2, 16'hFFFF, WORD); // verify reset
|
host.wb_cmp(0, IRQ_BYPS_2, 16'hFFFF, WORD); // verify reset
|
host.wb_cmp(0, IRQ_BYPS_3, 16'hFFFF, WORD); // verify reset
|
host.wb_cmp(0, IRQ_BYPS_3, 16'hFFFF, WORD); // verify reset
|
host.wb_cmp(0, IRQ_BYPS_4, 16'hFFFF, WORD); // verify reset
|
host.wb_cmp(0, IRQ_BYPS_4, 16'hFFFF, WORD); // verify reset
|
host.wb_cmp(0, IRQ_BYPS_5, 16'hFFFF, WORD); // verify reset
|
host.wb_cmp(0, IRQ_BYPS_5, 16'hFFFF, WORD); // verify reset
|
| Line 1025... |
Line 1025... |
|
|
// Test the Xgate IRQ Bypass Registers (IRQ_BYPS)
|
// Test the Xgate IRQ Bypass Registers (IRQ_BYPS)
|
host.wb_write(0, IRQ_BYPS_0, 16'hAAAA, WORD);
|
host.wb_write(0, IRQ_BYPS_0, 16'hAAAA, WORD);
|
host.wb_cmp(0, IRQ_BYPS_0, 16'hAAAA, WORD);
|
host.wb_cmp(0, IRQ_BYPS_0, 16'hAAAA, WORD);
|
host.wb_write(0, IRQ_BYPS_0, 16'h5555, WORD);
|
host.wb_write(0, IRQ_BYPS_0, 16'h5555, WORD);
|
host.wb_cmp(0, IRQ_BYPS_0, 16'h5555, WORD);
|
host.wb_cmp(0, IRQ_BYPS_0, 16'h5554, WORD);
|
|
|
host.wb_write(0, IRQ_BYPS_0, 16'hFF66, L_BYTE);
|
host.wb_write(0, IRQ_BYPS_0, 16'hFF66, L_BYTE);
|
host.wb_cmp(0, IRQ_BYPS_0, 16'h5566, WORD);
|
host.wb_cmp(0, IRQ_BYPS_0, 16'h5566, WORD);
|
host.wb_write(0, IRQ_BYPS_0, 16'h33FF, H_BYTE);
|
host.wb_write(0, IRQ_BYPS_0, 16'h33FF, H_BYTE);
|
host.wb_cmp(0, IRQ_BYPS_0, 16'h3366, WORD);
|
host.wb_cmp(0, IRQ_BYPS_0, 16'h3366, WORD);
|
| Line 1554... |
Line 1554... |
// Slave unique IO Signals
|
// Slave unique IO Signals
|
output reg error_pulse, // Error detected output pulse
|
output reg error_pulse, // Error detected output pulse
|
output reg ack_pulse, // Thread ack output pulse
|
output reg ack_pulse, // Thread ack output pulse
|
output brk_pt, // Break point
|
output brk_pt, // Break point
|
input [15:0] x_address, // XGATE WISHBONE Master bus address
|
input [15:0] x_address, // XGATE WISHBONE Master bus address
|
input [MAX_CHANNEL:0] xgif, // XGATE Interrupt Flag to Host
|
input [MAX_CHANNEL:1] xgif, // XGATE Interrupt Flag to Host
|
input [19:0] vector
|
input [19:0] vector
|
);
|
);
|
|
|
wire async_rst_b; // Asyncronous reset
|
wire async_rst_b; // Asyncronous reset
|
wire sync_reset; // Syncronous reset
|
wire sync_reset; // Syncronous reset
|
| Line 1623... |
Line 1623... |
4'b0001: rd_data_mux = channel_ack_reg;
|
4'b0001: rd_data_mux = channel_ack_reg;
|
4'b0010: rd_data_mux = channel_err_reg;
|
4'b0010: rd_data_mux = channel_err_reg;
|
4'b0011: rd_data_mux = brkpt_cntl_reg;
|
4'b0011: rd_data_mux = brkpt_cntl_reg;
|
4'b0100: rd_data_mux = brkpt_addr_reg;
|
4'b0100: rd_data_mux = brkpt_addr_reg;
|
4'b0101: rd_data_mux = tb_semaphr_reg;
|
4'b0101: rd_data_mux = tb_semaphr_reg;
|
4'b1000: rd_data_mux = xgif[15: 0];
|
4'b1000: rd_data_mux = {xgif[15: 1], 1'b0};
|
4'b1001: rd_data_mux = xgif[31:16];
|
4'b1001: rd_data_mux = xgif[31:16];
|
4'b1010: rd_data_mux = xgif[47:32];
|
4'b1010: rd_data_mux = xgif[47:32];
|
4'b1011: rd_data_mux = xgif[63:48];
|
4'b1011: rd_data_mux = xgif[63:48];
|
4'b1100: rd_data_mux = xgif[79:64];
|
4'b1100: rd_data_mux = xgif[79:64];
|
4'b1101: rd_data_mux = xgif[95:80];
|
4'b1101: rd_data_mux = xgif[95:80];
|
