| Line 100... |
Line 100... |
parameter XGMCTL_XGIE = 15'h0001;
|
parameter XGMCTL_XGIE = 15'h0001;
|
|
|
parameter CHECK_POINT = 16'h8000;
|
parameter CHECK_POINT = 16'h8000;
|
parameter CHANNEL_ACK = CHECK_POINT + 2;
|
parameter CHANNEL_ACK = CHECK_POINT + 2;
|
parameter CHANNEL_ERR = CHECK_POINT + 4;
|
parameter CHANNEL_ERR = CHECK_POINT + 4;
|
|
parameter DEBUG_CNTRL = CHECK_POINT + 6;
|
parameter TB_SEMPHORE = CHECK_POINT + 10;
|
parameter TB_SEMPHORE = CHECK_POINT + 10;
|
parameter CHANNEL_XGIRQ_0 = CHECK_POINT + 16;
|
parameter CHANNEL_XGIRQ_0 = CHECK_POINT + 16;
|
parameter CHANNEL_XGIRQ_1 = CHECK_POINT + 18;
|
parameter CHANNEL_XGIRQ_1 = CHECK_POINT + 18;
|
parameter CHANNEL_XGIRQ_2 = CHECK_POINT + 20;
|
parameter CHANNEL_XGIRQ_2 = CHECK_POINT + 20;
|
parameter CHANNEL_XGIRQ_3 = CHECK_POINT + 22;
|
parameter CHANNEL_XGIRQ_3 = CHECK_POINT + 22;
|
parameter CHANNEL_XGIRQ_4 = CHECK_POINT + 24;
|
parameter CHANNEL_XGIRQ_4 = CHECK_POINT + 24;
|
parameter CHANNEL_XGIRQ_5 = CHECK_POINT + 26;
|
parameter CHANNEL_XGIRQ_5 = CHECK_POINT + 26;
|
parameter CHANNEL_XGIRQ_6 = CHECK_POINT + 28;
|
parameter CHANNEL_XGIRQ_6 = CHECK_POINT + 28;
|
parameter CHANNEL_XGIRQ_7 = CHECK_POINT + 30;
|
parameter CHANNEL_XGIRQ_7 = CHECK_POINT + 30;
|
|
|
|
parameter BREAK_CAPT_0 = CHECK_POINT + 64;
|
|
parameter BREAK_CAPT_1 = CHECK_POINT + 66;
|
|
parameter BREAK_CAPT_2 = CHECK_POINT + 68;
|
|
parameter BREAK_CAPT_3 = CHECK_POINT + 70;
|
|
parameter BREAK_CAPT_4 = CHECK_POINT + 72;
|
|
parameter BREAK_CAPT_5 = CHECK_POINT + 74;
|
|
parameter BREAK_CAPT_6 = CHECK_POINT + 76;
|
|
parameter BREAK_CAPT_7 = CHECK_POINT + 78;
|
|
|
parameter SYS_RAM_BASE = 24'h00_0000;
|
parameter SYS_RAM_BASE = 24'h00_0000;
|
|
|
parameter RAM_WAIT_STATES = 1; // Number between 0 and 15
|
parameter RAM_WAIT_STATES = 1; // Number between 0 and 15
|
parameter SYS_READ_DELAY = 10;
|
parameter SYS_READ_DELAY = 10;
|
parameter XGATE_ACCESS_DELAY = SYS_READ_DELAY + RAM_WAIT_STATES;
|
parameter XGATE_ACCESS_DELAY = SYS_READ_DELAY + RAM_WAIT_STATES;
|
| Line 146... |
Line 156... |
|
|
reg [MAX_CHANNEL:1] channel_req; // XGATE Interrupt inputs
|
reg [MAX_CHANNEL:1] channel_req; // XGATE Interrupt inputs
|
wire [MAX_CHANNEL:1] xgif; // XGATE Interrupt outputs
|
wire [MAX_CHANNEL:1] xgif; // XGATE Interrupt outputs
|
wire [ 7:0] xgswt; // XGATE Software Trigger outputs
|
wire [ 7:0] xgswt; // XGATE Software Trigger outputs
|
wire xg_sw_irq; // Xgate Software Error interrupt
|
wire xg_sw_irq; // Xgate Software Error interrupt
|
|
wire [15:0] brkpt_cntl; //
|
|
|
|
|
wire [15:0] wbm_dat_o; // WISHBONE Master Mode data output from XGATE
|
wire [15:0] wbm_dat_o; // WISHBONE Master Mode data output from XGATE
|
wire [15:0] wbm_dat_i; // WISHBONE Master Mode data input to XGATE
|
wire [15:0] wbm_dat_i; // WISHBONE Master Mode data input to XGATE
|
wire [15:0] wbm_adr_o; // WISHBONE Master Mode address output from XGATE
|
wire [15:0] wbm_adr_o; // WISHBONE Master Mode address output from XGATE
|
| Line 416... |
Line 427... |
.wb_cyc_i( sys_cyc ),
|
.wb_cyc_i( sys_cyc ),
|
.wb_sel_i( sys_sel ),
|
.wb_sel_i( sys_sel ),
|
.wb_ack_o( tb_slave_ack ),
|
.wb_ack_o( tb_slave_ack ),
|
|
|
.ack_pulse( ack_pulse ),
|
.ack_pulse( ack_pulse ),
|
|
.brkpt_cntl( brkpt_cntl ),
|
.error_pulse( error_pulse ),
|
.error_pulse( error_pulse ),
|
.brk_pt( ),
|
.brk_pt( ),
|
.x_address( wbm_adr_o ),
|
.x_address( wbm_adr_o ),
|
.xgif( xgif ),
|
.xgif( xgif ),
|
.vector( vector )
|
.vector( vector )
|
);
|
);
|
|
|
|
tb_debug #(.DWIDTH(16), // Data bus width
|
|
.BREAK_CAPT_0(BREAK_CAPT_0),
|
|
.BREAK_CAPT_1(BREAK_CAPT_1),
|
|
.BREAK_CAPT_2(BREAK_CAPT_2),
|
|
.BREAK_CAPT_3(BREAK_CAPT_3),
|
|
.BREAK_CAPT_4(BREAK_CAPT_4),
|
|
.BREAK_CAPT_5(BREAK_CAPT_5),
|
|
.BREAK_CAPT_6(BREAK_CAPT_6),
|
|
.BREAK_CAPT_7(BREAK_CAPT_7))
|
|
debugger(
|
|
.arst_i( rstn ),
|
|
.risc_clk( mstr_test_clk ),
|
|
.brkpt_cntl( brkpt_cntl )
|
|
);
|
|
|
|
|
////////////////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////////////////
|
| Line 465... |
Line 491... |
|
|
reg_irq;
|
reg_irq;
|
|
|
// host_ram;
|
// host_ram;
|
|
|
|
// test_skipjack;
|
|
|
// End testing
|
// End testing
|
wrap_up;
|
wrap_up;
|
end
|
end
|
|
|
////////////////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////////////////
|
| Line 802... |
Line 830... |
|
|
end
|
end
|
endtask
|
endtask
|
|
|
////////////////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////////////////
|
|
// Test SKIPJACK Application Program
|
|
task test_skipjack;
|
|
begin
|
|
$readmemh("../../../bench/verilog/skipjack.v", p_ram.ram_8);
|
|
test_num = test_num + 1;
|
|
$display("\nTEST #%d Starts at vector=%d, test_skipjack", test_num, vector);
|
|
repeat(1) @(posedge mstr_test_clk);
|
|
|
|
host.wb_write(0, DEBUG_CNTRL, 16'hFFFF, WORD);
|
|
|
|
// Enable interrupts to RISC
|
|
host.wb_write(0, IRQ_BYPS_0, 16'h0000, WORD);
|
|
|
|
activate_thread_sw(2);
|
|
wait_irq_set(2);
|
|
host.wb_write(1, XGATE_XGIF_0, 16'h0002, WORD);
|
|
|
|
|
|
repeat(20) @(posedge mstr_test_clk);
|
|
|
|
p_ram.dump_ram(16'h2000);
|
|
// repeat(2) @(posedge mstr_test_clk);
|
|
// p_ram.dump_ram(16'h9000);
|
|
|
|
data_xgmctl = 16'hff00;
|
|
host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD); // Disable XGATE
|
|
|
|
end
|
|
endtask
|
|
|
|
////////////////////////////////////////////////////////////////////////////////
|
// check register bits - reset, read/write
|
// check register bits - reset, read/write
|
task reg_test_16;
|
task reg_test_16;
|
begin
|
begin
|
test_num = test_num + 1;
|
test_num = test_num + 1;
|
$display("\nTEST #%d Starts at vector=%d, reg_test_16", test_num, vector);
|
$display("\nTEST #%d Starts at vector=%d, reg_test_16", test_num, vector);
|
| Line 1552... |
Line 1611... |
input wb_cyc_i, // valid bus cycle input
|
input wb_cyc_i, // valid bus cycle input
|
input [1:0] wb_sel_i, // Select byte in word bus transaction
|
input [1:0] wb_sel_i, // Select byte in word bus transaction
|
// Slave unique IO Signals
|
// Slave unique IO Signals
|
output reg error_pulse, // Error detected output pulse
|
output reg error_pulse, // Error detected output pulse
|
output reg ack_pulse, // Thread ack output pulse
|
output reg ack_pulse, // Thread ack output pulse
|
|
output reg [DWIDTH-1:0] brkpt_cntl, // Break Point Control reg
|
|
|
output brk_pt, // Break point
|
output brk_pt, // Break point
|
input [15:0] x_address, // XGATE WISHBONE Master bus address
|
input [15:0] x_address, // XGATE WISHBONE Master bus address
|
input [MAX_CHANNEL:1] xgif, // XGATE Interrupt Flag to Host
|
input [MAX_CHANNEL:1] xgif, // XGATE Interrupt Flag to Host
|
input [19:0] vector
|
input [19:0] vector
|
);
|
);
|
| Line 1572... |
Line 1633... |
reg [DWIDTH-1:0] check_point_reg;
|
reg [DWIDTH-1:0] check_point_reg;
|
reg [DWIDTH-1:0] channel_ack_reg;
|
reg [DWIDTH-1:0] channel_ack_reg;
|
reg [DWIDTH-1:0] channel_err_reg;
|
reg [DWIDTH-1:0] channel_err_reg;
|
|
|
reg [DWIDTH-1:0] brkpt_addr_reg; // Break Point Address reg
|
reg [DWIDTH-1:0] brkpt_addr_reg; // Break Point Address reg
|
reg [DWIDTH-1:0] brkpt_cntl_reg; // Break Point Control reg
|
|
|
|
reg [DWIDTH-1:0] tb_semaphr_reg; // Test bench semaphore reg
|
reg [DWIDTH-1:0] tb_semaphr_reg; // Test bench semaphore reg
|
|
|
event check_point_wrt;
|
event check_point_wrt;
|
event channel_ack_wrt;
|
event channel_ack_wrt;
|
| Line 1620... |
Line 1680... |
always @*
|
always @*
|
case (wb_adr_i) // synopsys parallel_case
|
case (wb_adr_i) // synopsys parallel_case
|
4'b0000: rd_data_mux = check_point_reg;
|
4'b0000: rd_data_mux = check_point_reg;
|
4'b0001: rd_data_mux = channel_ack_reg;
|
4'b0001: rd_data_mux = channel_ack_reg;
|
4'b0010: rd_data_mux = channel_err_reg;
|
4'b0010: rd_data_mux = channel_err_reg;
|
4'b0011: rd_data_mux = brkpt_cntl_reg;
|
4'b0011: rd_data_mux = brkpt_cntl;
|
4'b0100: rd_data_mux = brkpt_addr_reg;
|
4'b0100: rd_data_mux = brkpt_addr_reg;
|
4'b0101: rd_data_mux = tb_semaphr_reg;
|
4'b0101: rd_data_mux = tb_semaphr_reg;
|
4'b1000: rd_data_mux = {xgif[15: 1], 1'b0};
|
4'b1000: rd_data_mux = {xgif[15: 1], 1'b0};
|
4'b1001: rd_data_mux = xgif[31:16];
|
4'b1001: rd_data_mux = xgif[31:16];
|
4'b1010: rd_data_mux = xgif[47:32];
|
4'b1010: rd_data_mux = xgif[47:32];
|
| Line 1644... |
Line 1704... |
check_point_reg <= 0;
|
check_point_reg <= 0;
|
channel_ack_reg <= 0;
|
channel_ack_reg <= 0;
|
channel_err_reg <= 0;
|
channel_err_reg <= 0;
|
ack_pulse <= 0;
|
ack_pulse <= 0;
|
error_pulse <= 0;
|
error_pulse <= 0;
|
brkpt_cntl_reg <= 0;
|
brkpt_cntl <= 0;
|
brkpt_addr_reg <= 0;
|
brkpt_addr_reg <= 0;
|
tb_semaphr_reg <= 0;
|
tb_semaphr_reg <= 0;
|
end
|
end
|
else if (wb_wacc)
|
else if (wb_wacc)
|
case (wb_adr_i) // synopsys parallel_case
|
case (wb_adr_i) // synopsys parallel_case
|
| Line 1672... |
Line 1732... |
error_pulse <= 1'b1;
|
error_pulse <= 1'b1;
|
-> channel_err_wrt;
|
-> channel_err_wrt;
|
end
|
end
|
3'b011 :
|
3'b011 :
|
begin
|
begin
|
brkpt_cntl_reg[ 7:0] <= wb_sel_i[0] ? wb_dat_i[ 7:0] : brkpt_cntl_reg[ 7:0];
|
brkpt_cntl[ 7:0] <= wb_sel_i[0] ? wb_dat_i[ 7:0] : brkpt_cntl[ 7:0];
|
brkpt_cntl_reg[15:8] <= wb_sel_i[1] ? wb_dat_i[15:8] : brkpt_cntl_reg[15:8];
|
brkpt_cntl[15:8] <= wb_sel_i[1] ? wb_dat_i[15:8] : brkpt_cntl[15:8];
|
end
|
end
|
3'b100 :
|
3'b100 :
|
begin
|
begin
|
brkpt_addr_reg[ 7:0] <= wb_sel_i[0] ? wb_dat_i[ 7:0] : brkpt_addr_reg[ 7:0];
|
brkpt_addr_reg[ 7:0] <= wb_sel_i[0] ? wb_dat_i[ 7:0] : brkpt_addr_reg[ 7:0];
|
brkpt_addr_reg[15:8] <= wb_sel_i[1] ? wb_dat_i[15:8] : brkpt_addr_reg[15:8];
|
brkpt_addr_reg[15:8] <= wb_sel_i[1] ? wb_dat_i[15:8] : brkpt_addr_reg[15:8];
|
| Line 1709... |
Line 1769... |
end
|
end
|
|
|
|
|
endmodule // tb_slave
|
endmodule // tb_slave
|
|
|
|
////////////////////////////////////////////////////////////////////////////////
|
|
////////////////////////////////////////////////////////////////////////////////
|
|
////////////////////////////////////////////////////////////////////////////////
|
|
module tb_debug #(parameter DWIDTH = 16, // Data bus width
|
|
parameter BREAK_CAPT_0 = 0,
|
|
parameter BREAK_CAPT_1 = 0,
|
|
parameter BREAK_CAPT_2 = 0,
|
|
parameter BREAK_CAPT_3 = 0,
|
|
parameter BREAK_CAPT_4 = 0,
|
|
parameter BREAK_CAPT_5 = 0,
|
|
parameter BREAK_CAPT_6 = 0,
|
|
parameter BREAK_CAPT_7 = 0
|
|
)
|
|
(
|
|
// Wishbone Signals
|
|
input arst_i, // asynchronous reset
|
|
input risc_clk,
|
|
input [DWIDTH-1:0] brkpt_cntl // databus input
|
|
);
|
|
|
|
wire [15:0] next_pc = xgate.risc.program_counter;
|
|
wire [15:0] x1 = xgate.risc.xgr1;
|
|
wire [15:0] x2 = xgate.risc.xgr2;
|
|
wire [15:0] x3 = xgate.risc.xgr3;
|
|
wire [15:0] x4 = xgate.risc.xgr4;
|
|
wire [15:0] x5 = xgate.risc.xgr5;
|
|
wire [15:0] x6 = xgate.risc.xgr6;
|
|
wire [15:0] x7 = xgate.risc.xgr7;
|
|
|
|
reg [15:0] cap_x1;
|
|
reg [15:0] cap_x2;
|
|
reg [15:0] cap_x3;
|
|
reg [15:0] cap_x4;
|
|
reg [15:0] cap_x5;
|
|
reg [15:0] cap_x6;
|
|
reg [15:0] cap_x7;
|
|
|
|
reg [15:0] break_addr_0;
|
|
reg [15:0] break_addr_1;
|
|
reg [15:0] break_addr_2;
|
|
reg [15:0] break_addr_3;
|
|
reg [15:0] break_addr_4;
|
|
reg [15:0] break_addr_5;
|
|
reg [15:0] break_addr_6;
|
|
reg [15:0] break_addr_7;
|
|
|
|
reg detect_addr;
|
|
|
|
wire trigger, trigger0, trigger1, trigger3, trigger4, trigger5, trigger6, trigger7;
|
|
|
|
initial
|
|
begin
|
|
break_addr_0 = 0;
|
|
break_addr_1 = 0;
|
|
break_addr_2 = 0;
|
|
break_addr_3 = 0;
|
|
break_addr_4 = 0;
|
|
break_addr_5 = 0;
|
|
break_addr_6 = 0;
|
|
break_addr_7 = 0;
|
|
repeat(4) @(posedge risc_clk); // Note: !! This should come after code load
|
|
break_addr_0 = {p_ram.ram_8[BREAK_CAPT_0], p_ram.ram_8[BREAK_CAPT_0+1]};
|
|
break_addr_1 = {p_ram.ram_8[BREAK_CAPT_1], p_ram.ram_8[BREAK_CAPT_1+1]};
|
|
break_addr_2 = {p_ram.ram_8[BREAK_CAPT_2], p_ram.ram_8[BREAK_CAPT_2+1]};
|
|
break_addr_3 = {p_ram.ram_8[BREAK_CAPT_3], p_ram.ram_8[BREAK_CAPT_3+1]};
|
|
break_addr_4 = {p_ram.ram_8[BREAK_CAPT_4], p_ram.ram_8[BREAK_CAPT_4+1]};
|
|
break_addr_5 = {p_ram.ram_8[BREAK_CAPT_5], p_ram.ram_8[BREAK_CAPT_5+1]};
|
|
break_addr_6 = {p_ram.ram_8[BREAK_CAPT_6], p_ram.ram_8[BREAK_CAPT_6+1]};
|
|
break_addr_7 = {p_ram.ram_8[BREAK_CAPT_7], p_ram.ram_8[BREAK_CAPT_7+1]};
|
|
end
|
|
|
|
assign trigger0 = (next_pc === break_addr_0) && brkpt_cntl[ 8];
|
|
assign trigger1 = (next_pc === break_addr_1) && brkpt_cntl[ 9];
|
|
assign trigger2 = (next_pc === break_addr_2) && brkpt_cntl[10];
|
|
assign trigger3 = (next_pc === break_addr_3) && brkpt_cntl[11];
|
|
assign trigger4 = (next_pc === break_addr_4) && brkpt_cntl[12];
|
|
assign trigger5 = (next_pc === break_addr_5) && brkpt_cntl[13];
|
|
assign trigger6 = (next_pc === break_addr_6) && brkpt_cntl[14];
|
|
assign trigger7 = (next_pc === break_addr_7) && brkpt_cntl[15];
|
|
|
|
assign trigger = brkpt_cntl[0] &
|
|
(trigger0 | trigger1 | trigger2 | trigger3 | trigger4 | trigger5 | trigger6 | trigger7);
|
|
|
|
always @(posedge risc_clk or negedge arst_i)
|
|
begin
|
|
if (!arst_i)
|
|
begin
|
|
cap_x1 <= 0;
|
|
cap_x2 <= 0;
|
|
cap_x3 <= 0;
|
|
cap_x4 <= 0;
|
|
cap_x5 <= 0;
|
|
cap_x6 <= 0;
|
|
cap_x7 <= 0;
|
|
end
|
|
else if (trigger)
|
|
begin
|
|
cap_x1 <= x1;
|
|
cap_x2 <= x2;
|
|
cap_x3 <= x3;
|
|
cap_x4 <= x4;
|
|
cap_x5 <= x5;
|
|
cap_x6 <= x6;
|
|
cap_x7 <= x7;
|
|
end
|
|
end
|
|
|
|
|
|
endmodule // tb_debug
|
|
|
|
|
No newline at end of file
|
No newline at end of file
|
