| Line 45... |
Line 45... |
|
|
parameter MAX_CHANNEL = 127; // Max XGATE Interrupt Channel Number
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parameter MAX_CHANNEL = 127; // Max XGATE Interrupt Channel Number
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parameter STOP_ON_ERROR = 1'b0;
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parameter STOP_ON_ERROR = 1'b0;
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parameter MAX_VECTOR = 9000;
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parameter MAX_VECTOR = 9000;
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|
|
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parameter IR_BITS = 4; // Number of bits in JTAG instruction
|
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parameter JTAG_PERIOD = 4; // JTAG Test clock half period
|
|
|
parameter L_BYTE = 2'b01;
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parameter L_BYTE = 2'b01;
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parameter H_BYTE = 2'b10;
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parameter H_BYTE = 2'b10;
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parameter WORD = 2'b11;
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parameter WORD = 2'b11;
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|
|
|
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| Line 152... |
Line 155... |
reg rstn;
|
reg rstn;
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reg sync_reset;
|
reg sync_reset;
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reg por_reset_b;
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reg por_reset_b;
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reg scantestmode;
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reg scantestmode;
|
|
|
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reg jtag_tck;
|
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reg jtag_tdi;
|
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reg jtag_tms;
|
|
|
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wire jtag_tdo;
|
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wire jtag_tdo_en;
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|
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reg [MAX_CHANNEL:1] channel_req; // XGATE Interrupt inputs
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reg [MAX_CHANNEL:1] channel_req; // XGATE Interrupt inputs
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wire [MAX_CHANNEL:1] xgif; // XGATE Interrupt outputs
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wire [MAX_CHANNEL:1] xgif; // XGATE Interrupt outputs
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wire [ 7:0] xgswt; // XGATE Software Trigger outputs
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wire [ 7:0] xgswt; // XGATE Software Trigger outputs
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wire xg_sw_irq; // Xgate Software Error interrupt
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wire xg_sw_irq; // Xgate Software Error interrupt
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wire [15:0] brkpt_cntl; //
|
wire [15:0] brkpt_cntl; //
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| Line 230... |
Line 240... |
test_num = 0;
|
test_num = 0;
|
por_reset_b = 0;
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por_reset_b = 0;
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scantestmode = 0;
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scantestmode = 0;
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error_count = 0;
|
error_count = 0;
|
mem_wait_state_enable = 0;
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mem_wait_state_enable = 0;
|
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jtag_tck = 0;
|
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jtag_tdi = 0;
|
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jtag_tms = 1;
|
|
|
// channel_req = 0;
|
// channel_req = 0;
|
|
|
`ifdef WAVES
|
`ifdef WAVES
|
$shm_open("waves");
|
$shm_open("waves");
|
$shm_probe("AS",tst_bench_top,"AS");
|
$shm_probe("AS",tst_bench_top,"AS");
|
| Line 409... |
Line 423... |
.debug_mode_i( 1'b0 ),
|
.debug_mode_i( 1'b0 ),
|
.secure_mode_i( 1'b0 ),
|
.secure_mode_i( 1'b0 ),
|
.scantestmode( scantestmode )
|
.scantestmode( scantestmode )
|
);
|
);
|
|
|
|
xgate_jtag #(.IR_BITS(IR_BITS))
|
|
jtag(
|
|
.jtag_tdo( jtag_tdo ),
|
|
.jtag_tdo_en( jtag_tdo_en ),
|
|
|
|
.jtag_tdi( jtag_tdi ),
|
|
.jtag_clk( jtag_tck ),
|
|
.jtag_reset_n( rstn ),
|
|
.jtag_tms( jtag_tms )
|
|
);
|
|
|
|
|
tb_slave #(.DWIDTH(16),
|
tb_slave #(.DWIDTH(16),
|
.SINGLE_CYCLE(1'b1),
|
.SINGLE_CYCLE(1'b1),
|
.MAX_CHANNEL(MAX_CHANNEL))
|
.MAX_CHANNEL(MAX_CHANNEL))
|
tb_slave_regs(
|
tb_slave_regs(
|
// wishbone interface
|
// wishbone interface
|
| Line 497... |
Line 523... |
|
|
// End testing
|
// End testing
|
wrap_up;
|
wrap_up;
|
end
|
end
|
|
|
|
// Main JTAG Test Program
|
|
initial
|
|
begin
|
|
$display("\nstatus at time: %t Testbench started", $time);
|
|
// tms, tdi
|
|
send_jtag_bit(1,0); // RUN/TEST/IDLE
|
|
send_jtag_bit(0,1); // SEL DR
|
|
send_jtag_bit(1,1); // SEL IR
|
|
send_jtag_bit(1,1); // Capture IR
|
|
send_jtag_bit(0,1); // Dead Bit?
|
|
send_jtag_bit(0,1); // LSB
|
|
send_jtag_bit(0,0); // Bit 1
|
|
send_jtag_bit(0,1); // Bit 2
|
|
send_jtag_bit(0,0); // Bit 3
|
|
send_jtag_bit(1,1); // EXIT1 IR
|
|
send_jtag_bit(1,1); // UPDATE IR
|
|
send_jtag_bit(0,1); // RUN/TEST/IDLE
|
|
send_jtag_bit(0,1); // RUN/TEST/IDLE
|
|
|
|
end
|
|
|
////////////////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////////////////
|
// Test CHID Debug mode operation
|
// Test CHID Debug mode operation
|
task test_chid_debug;
|
task test_chid_debug;
|
begin
|
begin
|
test_num = test_num + 1;
|
test_num = test_num + 1;
|
| Line 1336... |
Line 1383... |
$finish;
|
$finish;
|
end
|
end
|
endtask
|
endtask
|
|
|
////////////////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////////////////
|
|
task send_jtag_bit;
|
|
input tms_val;
|
|
input tdi_val;
|
|
begin
|
|
jtag_tck = 0;
|
|
repeat(JTAG_PERIOD) @(posedge mstr_test_clk);
|
|
jtag_tck = 1;
|
|
#1;
|
|
jtag_tms = tms_val;
|
|
jtag_tdi = tdi_val;
|
|
repeat(JTAG_PERIOD) @(posedge mstr_test_clk);
|
|
jtag_tck = 0;
|
|
end
|
|
endtask
|
|
|
|
////////////////////////////////////////////////////////////////////////////////
|
function [15:0] four_2_16;
|
function [15:0] four_2_16;
|
input [3:0] vector;
|
input [3:0] vector;
|
begin
|
begin
|
case (vector)
|
case (vector)
|
4'h0 : four_2_16 = 16'b0000_0000_0000_0001;
|
4'h0 : four_2_16 = 16'b0000_0000_0000_0001;
|
