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[/] [xgate/] [trunk/] [bench/] [verilog/] [tst_bench_top.v] - Diff between revs 86 and 89

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Rev 86 Rev 89
Line 43... Line 43... 
 
 
 
 
module tst_bench_top();
 
module tst_bench_top();
 
 
 
 
 
  parameter MAX_CHANNEL = 127;    // Max XGATE Interrupt Channel Number
 
  parameter MAX_CHANNEL = 127;    // Max XGATE Interrupt Channel Number
 
  parameter STOP_ON_ERROR = 1'b0;
 
  parameter STOP_ON_ERROR = 1'b0;
 
  parameter MAX_VECTOR = 9000;
 
  parameter MAX_VECTOR    = 12_000;
 
 
 
 
 
  parameter IR_BITS = 4;     // Number of bits in JTAG instruction
 
 
 
  parameter JTAG_PERIOD = 4; // JTAG Test clock half period
 
 
 
 
 
 
 
  parameter L_BYTE = 2'b01;
 
  parameter L_BYTE = 2'b01;
 
  parameter H_BYTE = 2'b10;
 
  parameter H_BYTE = 2'b10;
 
  parameter WORD   = 2'b11;
 
  parameter WORD   = 2'b11;
 
 
 
 
Line 155... Line 152... 
  reg         rstn;
 
  reg         rstn;
 
  reg         sync_reset;
 
  reg         sync_reset;
 
  reg         por_reset_b;
 
  reg         por_reset_b;
 
  reg         scantestmode;
 
  reg         scantestmode;
 
 
 
 
 
  reg         jtag_tck;
 
 
 
  reg         jtag_tdi;
 
 
 
  reg         jtag_tms;
 
 
 
 
 
 
 
  wire        jtag_tdo;
 
 
 
  wire        jtag_tdo_en;
 
 
 
 
 
 
 
  reg  [MAX_CHANNEL:1] channel_req;  // XGATE Interrupt inputs
 
  reg  [MAX_CHANNEL:1] channel_req;  // XGATE Interrupt inputs
 
  wire [MAX_CHANNEL:1] xgif;         // XGATE Interrupt outputs
 
  wire [MAX_CHANNEL:1] xgif;         // XGATE Interrupt outputs
 
  wire         [  7:0] xgswt;         // XGATE Software Trigger outputs
 
  wire         [  7:0] xgswt;         // XGATE Software Trigger outputs
 
  wire                 xg_sw_irq;    // Xgate Software Error interrupt
 
  wire                 xg_sw_irq;    // Xgate Software Error interrupt
 
  wire          [15:0] brkpt_cntl;   // 
  wire          [15:0] brkpt_cntl;   //
Line 240... Line 230... 
      test_num = 0;
 
      test_num = 0;
 
      por_reset_b = 0;
 
      por_reset_b = 0;
 
      scantestmode = 0;
 
      scantestmode = 0;
 
      error_count = 0;
 
      error_count = 0;
 
      mem_wait_state_enable = 0;
 
      mem_wait_state_enable = 0;
 
      jtag_tck = 0;
 
 
 
      jtag_tdi = 0;
 
 
 
      jtag_tms = 1;
 
 
 
 
 
 
 
      // channel_req = 0;
 
      // channel_req = 0;
 
 
 
 
 
      `ifdef WAVES
 
      `ifdef WAVES
 
           $shm_open("waves");
 
           $shm_open("waves");
 
           $shm_probe("AS",tst_bench_top,"AS");
 
           $shm_probe("AS",tst_bench_top,"AS");
Line 259... Line 245... 
           $dumpvars (0, tst_bench_top);
 
           $dumpvars (0, tst_bench_top);
 
           $dumpon;
 
           $dumpon;
 
           $display("\nINFO: VCD Signal dump enabled ...\n\n");
 
           $display("\nINFO: VCD Signal dump enabled ...\n\n");
 
      `endif
 
      `endif
 
 
 
 
 
 
 
      //-------------------------------------------------------
 
 
 
      // Enable Debussy dumping of simulation
 
 
 
      `ifdef FSDB
 
 
 
         $fsdbDumpfile("verilog.fsdb");
 
 
 
         $fsdbDumpvars(0, tst_bench_top);
 
 
 
      `endif
 
 
 
 
 
    end
 
    end
 
 
 
 
 
  // generate clock
 
  // generate clock
 
  always #20 mstr_test_clk = ~mstr_test_clk;
 
  always #20 mstr_test_clk = ~mstr_test_clk;
 
 
 
 
Line 423... Line 416... 
          .debug_mode_i( 1'b0 ),
 
          .debug_mode_i( 1'b0 ),
 
          .secure_mode_i( 1'b0 ),
 
          .secure_mode_i( 1'b0 ),
 
          .scantestmode( scantestmode )
 
          .scantestmode( scantestmode )
 
  );
 
  );
 
 
 
 
 
  xgate_jtag #(.IR_BITS(IR_BITS))
 
 
 
  jtag(
 
 
 
  .jtag_tdo( jtag_tdo ),
 
 
 
  .jtag_tdo_en( jtag_tdo_en ),
 
 
 
 
 
 
 
  .jtag_tdi( jtag_tdi ),
 
 
 
  .jtag_clk( jtag_tck ),
 
 
 
  .jtag_reset_n( rstn ),
 
 
 
  .jtag_tms( jtag_tms )
 
 
 
  );
 
 
 
 
 
 
 
 
 
 
 
  tb_slave #(.DWIDTH(16),
 
  tb_slave #(.DWIDTH(16),
 
             .SINGLE_CYCLE(1'b1),
 
             .SINGLE_CYCLE(1'b1),
 
             .MAX_CHANNEL(MAX_CHANNEL))
 
             .MAX_CHANNEL(MAX_CHANNEL))
 
          tb_slave_regs(
 
          tb_slave_regs(
 
          // wishbone interface
 
          // wishbone interface
Line 503... Line 484... 
    sync_reset = 1'b0;
 
    sync_reset = 1'b0;
 
    channel_req = 0; //
 
    channel_req = 0; //
 
 
 
 
 
    $display("\nstatus at time: %t done reset", $time);
 
    $display("\nstatus at time: %t done reset", $time);
 
 
 
 
 
 
 
    test_skipjack;
 
 
 
 
 
    test_inst_set;
 
    test_inst_set;
 
 
 
 
 
    test_debug_mode;
 
    test_debug_mode;
 
 
 
 
 
    test_debug_bit;
 
    test_debug_bit;
Line 517... Line 500... 
 
 
 
 
    reg_irq;
 
    reg_irq;
 
 
 
 
 
    // host_ram;
 
    // host_ram;
 
 
 
 
 
    // test_skipjack;
 
 
 
 
 
 
 
    // End testing
 
    // End testing
 
    wrap_up;
 
    wrap_up;
 
  end
 
  end
 
 
 
 
 
// Main JTAG Test Program
 
 
 
initial
 
 
 
  begin
 
 
 
    $display("\nstatus at time: %t Testbench started", $time);
 
 
 
  //              tms, tdi
 
 
 
    send_jtag_bit(1,0);  // RUN/TEST/IDLE
 
 
 
    send_jtag_bit(0,1);  // SEL DR
 
 
 
    send_jtag_bit(1,1);  // SEL IR
 
 
 
    send_jtag_bit(1,1);  // Capture IR
 
 
 
    send_jtag_bit(0,1);  // Dead Bit?
 
 
 
    send_jtag_bit(0,1);  // LSB
 
 
 
    send_jtag_bit(0,0);  // Bit 1
 
 
 
    send_jtag_bit(0,1);  // Bit 2
 
 
 
    send_jtag_bit(0,0);  // Bit 3
 
 
 
    send_jtag_bit(1,1);  // EXIT1 IR
 
 
 
    send_jtag_bit(1,1);  // UPDATE IR
 
 
 
    send_jtag_bit(0,1);  // RUN/TEST/IDLE    
 
 
    send_jtag_bit(0,1);  // RUN/TEST/IDLE    
 
 
 
 
 
 
  end
 
 
 
 
 
 
 
////////////////////////////////////////////////////////////////////////////////
 
////////////////////////////////////////////////////////////////////////////////
 
// Test CHID Debug mode operation
 
// Test CHID Debug mode operation
 
task test_chid_debug;
 
task test_chid_debug;
 
  begin
 
  begin
 
    test_num = test_num + 1;
 
    test_num = test_num + 1;
Line 669... Line 629... 
 
 
 
 
    host.wb_read(1, XGATE_XGR3, q, WORD);
 
    host.wb_read(1, XGATE_XGR3, q, WORD);
 
    data_xgmctl = XGMCTL_XGSSM | XGMCTL_XGSS;
 
    data_xgmctl = XGMCTL_XGSSM | XGMCTL_XGSS;
 
    qq = q;
 
    qq = q;
 
 
 
 
 
    // The Xgate test program is in an infinate loop incrementing R3
 
    // The Xgate test program is in an infinite loop incrementing R3
 
    while (qq == q)  // Look for change in R3 register
 
    while (qq == q)  // Look for change in R3 register
 
      begin
 
      begin
 
        host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD);   // Do a Single Step
 
        host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD);   // Do a Single Step
 
        repeat(XGATE_SS_DELAY) @(posedge mstr_test_clk);
 
        repeat(XGATE_SS_DELAY) @(posedge mstr_test_clk);
 
        host.wb_read(1, XGATE_XGR3, q, WORD);
 
        host.wb_read(1, XGATE_XGR3, q, WORD);
Line 869... Line 829... 
    read_ram_cmp(16'h0068,16'h2fcc);
 
    read_ram_cmp(16'h0068,16'h2fcc);
 
    read_ram_cmp(16'h0022,16'hccxx);
 
    read_ram_cmp(16'h0022,16'hccxx);
 
    read_ram_cmp(16'h0026,16'hxx99);
 
    read_ram_cmp(16'h0026,16'hxx99);
 
    read_ram_cmp(16'h0052,16'hxx66);
 
    read_ram_cmp(16'h0052,16'hxx66);
 
    read_ram_cmp(16'h0058,16'h99xx);
 
    read_ram_cmp(16'h0058,16'h99xx);
 
 
 
    read_ram_cmp(16'h0080, 16'h9966);
 
 
 
    read_ram_cmp(16'h0086, 16'h7533);
 
 
 
 
 
    data_xgmctl = 16'hff00;
 
    data_xgmctl = 16'hff00;
 
    host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD);    // Disable XGATE
 
    host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD);    // Disable XGATE
 
 
 
 
 
  end
 
  end
 
endtask
 
endtask
 
 
 
 
 
////////////////////////////////////////////////////////////////////////////////
 
////////////////////////////////////////////////////////////////////////////////
 
// Test SKIPJACK Application Program
 
// Test instruction set
 
task test_skipjack;
 
task test_skipjack;
 
  begin
 
  begin
 
    $readmemh("../../../bench/verilog/skipjack.v", p_ram.ram_8);
 
    $readmemh("../../../bench/verilog/skipjack.v", p_ram.ram_8);
 
    test_num = test_num + 1;
 
    test_num = test_num + 1;
 
    $display("\nTEST #%d Starts at vector=%d, test_skipjack", test_num, vector);
 
    $display("\nTEST #%d Starts at vector=%d, test_skipjack", test_num, vector);
Line 941... Line 903... 
    host.wb_cmp(0, XGATE_XGR4,     16'h0000, WORD);      // verify reset
 
    host.wb_cmp(0, XGATE_XGR4,     16'h0000, WORD);      // verify reset
 
    host.wb_cmp(0, XGATE_XGR5,     16'h0000, WORD);      // verify reset
 
    host.wb_cmp(0, XGATE_XGR5,     16'h0000, WORD);      // verify reset
 
    host.wb_cmp(0, XGATE_XGR6,     16'h0000, WORD);      // verify reset
 
    host.wb_cmp(0, XGATE_XGR6,     16'h0000, WORD);      // verify reset
 
    host.wb_cmp(0, XGATE_XGR7,     16'h0000, WORD);      // verify reset
 
    host.wb_cmp(0, XGATE_XGR7,     16'h0000, WORD);      // verify reset
 
 
 
 
 
/*
 
 
 
  parameter XGMCTL_XGDBGM   = 15'h2000;
 
 
 
  parameter XGMCTL_XGSSM    = 15'h1000;
 
 
 
  parameter XGMCTL_XGBRKIEM = 15'h0400;
 
 
 
  parameter XGMCTL_XGSWEIFM = 15'h0200;
 
 
 
  parameter XGMCTL_XGIEM    = 15'h0100;
 
 
 
 
 
 
 
  parameter XGMCTL_XGDBG    = 15'h0020;
 
 
 
  parameter XGMCTL_XGSS     = 15'h0010;
 
 
 
  parameter XGMCTL_XGBRKIE  = 15'h0004;
 
 
 
  parameter XGMCTL_XGSWEIF  = 15'h0002;
 
 
 
  parameter XGMCTL_XGIE     = 15'h0001;
 
 
 
*/
 
 
 
    // Test bits in the Xgate Control Register (XGMCTL)
 
    // Test bits in the Xgate Control Register (XGMCTL)
 
    data_xgmctl = XGMCTL_XGEM | XGMCTL_XGFRZM | XGMCTL_XGFACTM | XGMCTL_XGFRZ | XGMCTL_XGFACT | XGMCTL_XGE;
 
    data_xgmctl = XGMCTL_XGEM | XGMCTL_XGFRZM | XGMCTL_XGFACTM | XGMCTL_XGFRZ | XGMCTL_XGFACT | XGMCTL_XGE;
 
    host.wb_write(0, XGATE_XGMCTL,   data_xgmctl, WORD);   //
 
    host.wb_write(0, XGATE_XGMCTL,   data_xgmctl, WORD);   //
 
    data_xgmctl = XGMCTL_XGFRZ | XGMCTL_XGFACT | XGMCTL_XGE;
 
    data_xgmctl = XGMCTL_XGFRZ | XGMCTL_XGFACT | XGMCTL_XGE;
 
    host.wb_cmp(  0, XGATE_XGMCTL, data_xgmctl, WORD);
 
    host.wb_cmp(  0, XGATE_XGMCTL, data_xgmctl, WORD);
Line 1155... Line 1104... 
    host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD);   // Enable XGATE
 
    host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD);   // Enable XGATE
 
    repeat(XGATE_ACCESS_DELAY+2) @(posedge mstr_test_clk);
 
    repeat(XGATE_ACCESS_DELAY+2) @(posedge mstr_test_clk);
 
    channel_req[3:1] = 3'b111; //
 
    channel_req[3:1] = 3'b111; //
 
 
 
 
 
    q = 0;
 
    q = 0;
 
    // The Xgate test program is in an infinate loop for the test bench semaphore register to be changed
 
    // The Xgate test program is in an infinite loop for the test bench semaphore register to be changed
 
    while (q == 0)  // Look for change in test bench semapore register
 
    while (q == 0)  // Look for change in test bench semapore register
 
      begin
 
      begin
 
        host.wb_read(1, TB_SEMPHORE, q, WORD);
 
        host.wb_read(1, TB_SEMPHORE, q, WORD);
 
      end
 
      end
 
 
 
 
Line 1177... Line 1126... 
//    host.wb_cmp(0, XGATE_XGIF_0,    16'h0002, WORD);  // Verify Xgate interrupt status bit set
 
//    host.wb_cmp(0, XGATE_XGIF_0,    16'h0002, WORD);  // Verify Xgate interrupt status bit set
 
    host.wb_write(1, XGATE_XGIF_0, 16'h0002, WORD);  // Clear Interrupt Flag from Xgate
 
    host.wb_write(1, XGATE_XGIF_0, 16'h0002, WORD);  // Clear Interrupt Flag from Xgate
 
//    host.wb_cmp(0, XGATE_XGIF_0,    16'h0000, WORD);  // Verify flag cleared
 
//    host.wb_cmp(0, XGATE_XGIF_0,    16'h0000, WORD);  // Verify flag cleared
 
 
 
 
 
    q = 0;
 
    q = 0;
 
    // The Xgate test program is in an infinate loop for the test bench semaphore register to be changed
 
    // The Xgate test program is in an infinite loop for the test bench semaphore register to be changed
 
    while (q == 0)  // Look for change in test bench semapore register
 
    while (q == 0)  // Look for change in test bench semapore register
 
      begin
 
      begin
 
        host.wb_read(1, TB_SEMPHORE, q, WORD);
 
        host.wb_read(1, TB_SEMPHORE, q, WORD);
 
      end
 
      end
 
 
 
 
Line 1199... Line 1148... 
//    host.wb_cmp(0, XGATE_XGIF_0,    16'h0002, WORD);  // Verify Xgate interrupt status bit set
 
//    host.wb_cmp(0, XGATE_XGIF_0,    16'h0002, WORD);  // Verify Xgate interrupt status bit set
 
    host.wb_write(1, XGATE_XGIF_0, 16'h0004, WORD);  // Clear Interrupt Flag from Xgate
 
    host.wb_write(1, XGATE_XGIF_0, 16'h0004, WORD);  // Clear Interrupt Flag from Xgate
 
//    host.wb_cmp(0, XGATE_XGIF_0,    16'h0000, WORD);  // Verify flag cleared
 
//    host.wb_cmp(0, XGATE_XGIF_0,    16'h0000, WORD);  // Verify flag cleared
 
 
 
 
 
    q = 0;
 
    q = 0;
 
    // The Xgate test program is in an infinate loop for the test bench semaphore register to be changed
 
    // The Xgate test program is in an infinite loop for the test bench semaphore register to be changed
 
    while (q == 0)  // Look for change in test bench semapore register
 
    while (q == 0)  // Look for change in test bench semapore register
 
      begin
 
      begin
 
        host.wb_read(1, TB_SEMPHORE, q, WORD);
 
        host.wb_read(1, TB_SEMPHORE, q, WORD);
 
      end
 
      end
 
 
 
 
Line 1383... Line 1332... 
    $finish;
 
    $finish;
 
  end
 
  end
 
endtask
 
endtask
 
 
 
 
 
////////////////////////////////////////////////////////////////////////////////
 
////////////////////////////////////////////////////////////////////////////////
 
task send_jtag_bit;
 
 
 
  input tms_val;
 
 
 
  input tdi_val;
 
 
 
  begin
 
 
 
        jtag_tck = 0;
 
 
 
        repeat(JTAG_PERIOD) @(posedge mstr_test_clk);
 
 
 
        jtag_tck = 1;
 
 
 
        #1;
 
 
 
        jtag_tms = tms_val;
 
 
 
        jtag_tdi = tdi_val;
 
 
 
        repeat(JTAG_PERIOD) @(posedge mstr_test_clk);
 
 
 
        jtag_tck = 0;
 
 
 
  end
 
 
 
endtask
 
 
 
 
 
 
 
////////////////////////////////////////////////////////////////////////////////
 
 
 
function [15:0] four_2_16;
 
function [15:0] four_2_16;
 
  input [3:0] vector;
 
  input [3:0] vector;
 
  begin
 
  begin
 
    case (vector)
 
    case (vector)
 
      4'h0 : four_2_16 = 16'b0000_0000_0000_0001;
 
      4'h0 : four_2_16 = 16'b0000_0000_0000_0001;
Line 1892... Line 1825... 
      break_addr_3 = 0;
 
      break_addr_3 = 0;
 
      break_addr_4 = 0;
 
      break_addr_4 = 0;
 
      break_addr_5 = 0;
 
      break_addr_5 = 0;
 
      break_addr_6 = 0;
 
      break_addr_6 = 0;
 
      break_addr_7 = 0;
 
      break_addr_7 = 0;
 
      repeat(4) @(posedge risc_clk); // Note: !! This should come after code load
 
      repeat(4) @(posedge risc_clk);
 
      break_addr_0 = {p_ram.ram_8[BREAK_CAPT_0], p_ram.ram_8[BREAK_CAPT_0+1]};
 
      break_addr_0 = {p_ram.ram_8[BREAK_CAPT_0], p_ram.ram_8[BREAK_CAPT_0+1]};
 
      break_addr_1 = {p_ram.ram_8[BREAK_CAPT_1], p_ram.ram_8[BREAK_CAPT_1+1]};
 
      break_addr_1 = {p_ram.ram_8[BREAK_CAPT_1], p_ram.ram_8[BREAK_CAPT_1+1]};
 
      break_addr_2 = {p_ram.ram_8[BREAK_CAPT_2], p_ram.ram_8[BREAK_CAPT_2+1]};
 
      break_addr_2 = {p_ram.ram_8[BREAK_CAPT_2], p_ram.ram_8[BREAK_CAPT_2+1]};
 
      break_addr_3 = {p_ram.ram_8[BREAK_CAPT_3], p_ram.ram_8[BREAK_CAPT_3+1]};
 
      break_addr_3 = {p_ram.ram_8[BREAK_CAPT_3], p_ram.ram_8[BREAK_CAPT_3+1]};
 
      break_addr_4 = {p_ram.ram_8[BREAK_CAPT_4], p_ram.ram_8[BREAK_CAPT_4+1]};
 
      break_addr_4 = {p_ram.ram_8[BREAK_CAPT_4], p_ram.ram_8[BREAK_CAPT_4+1]};

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