Line 43... |
Line 43... |
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module tst_bench_top();
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module tst_bench_top();
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|
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parameter MAX_CHANNEL = 127; // Max XGATE Interrupt Channel Number
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parameter MAX_CHANNEL = 127; // Max XGATE Interrupt Channel Number
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parameter STOP_ON_ERROR = 1'b0;
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parameter STOP_ON_ERROR = 1'b0;
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parameter MAX_VECTOR = 9000;
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parameter MAX_VECTOR = 12_000;
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parameter IR_BITS = 4; // Number of bits in JTAG instruction
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parameter JTAG_PERIOD = 4; // JTAG Test clock half period
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parameter L_BYTE = 2'b01;
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parameter L_BYTE = 2'b01;
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parameter H_BYTE = 2'b10;
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parameter H_BYTE = 2'b10;
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parameter WORD = 2'b11;
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parameter WORD = 2'b11;
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Line 155... |
Line 152... |
reg rstn;
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reg rstn;
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reg sync_reset;
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reg sync_reset;
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reg por_reset_b;
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reg por_reset_b;
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reg scantestmode;
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reg scantestmode;
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reg jtag_tck;
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reg jtag_tdi;
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reg jtag_tms;
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wire jtag_tdo;
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wire jtag_tdo_en;
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reg [MAX_CHANNEL:1] channel_req; // XGATE Interrupt inputs
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reg [MAX_CHANNEL:1] channel_req; // XGATE Interrupt inputs
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wire [MAX_CHANNEL:1] xgif; // XGATE Interrupt outputs
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wire [MAX_CHANNEL:1] xgif; // XGATE Interrupt outputs
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wire [ 7:0] xgswt; // XGATE Software Trigger outputs
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wire [ 7:0] xgswt; // XGATE Software Trigger outputs
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wire xg_sw_irq; // Xgate Software Error interrupt
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wire xg_sw_irq; // Xgate Software Error interrupt
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wire [15:0] brkpt_cntl; //
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wire [15:0] brkpt_cntl; //
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Line 240... |
Line 230... |
test_num = 0;
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test_num = 0;
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por_reset_b = 0;
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por_reset_b = 0;
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scantestmode = 0;
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scantestmode = 0;
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error_count = 0;
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error_count = 0;
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mem_wait_state_enable = 0;
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mem_wait_state_enable = 0;
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jtag_tck = 0;
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jtag_tdi = 0;
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jtag_tms = 1;
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// channel_req = 0;
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// channel_req = 0;
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`ifdef WAVES
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`ifdef WAVES
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$shm_open("waves");
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$shm_open("waves");
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$shm_probe("AS",tst_bench_top,"AS");
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$shm_probe("AS",tst_bench_top,"AS");
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Line 259... |
Line 245... |
$dumpvars (0, tst_bench_top);
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$dumpvars (0, tst_bench_top);
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$dumpon;
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$dumpon;
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$display("\nINFO: VCD Signal dump enabled ...\n\n");
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$display("\nINFO: VCD Signal dump enabled ...\n\n");
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`endif
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`endif
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//-------------------------------------------------------
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// Enable Debussy dumping of simulation
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`ifdef FSDB
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$fsdbDumpfile("verilog.fsdb");
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$fsdbDumpvars(0, tst_bench_top);
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`endif
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end
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end
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// generate clock
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// generate clock
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always #20 mstr_test_clk = ~mstr_test_clk;
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always #20 mstr_test_clk = ~mstr_test_clk;
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Line 423... |
Line 416... |
.debug_mode_i( 1'b0 ),
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.debug_mode_i( 1'b0 ),
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.secure_mode_i( 1'b0 ),
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.secure_mode_i( 1'b0 ),
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.scantestmode( scantestmode )
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.scantestmode( scantestmode )
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);
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);
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xgate_jtag #(.IR_BITS(IR_BITS))
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jtag(
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.jtag_tdo( jtag_tdo ),
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.jtag_tdo_en( jtag_tdo_en ),
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.jtag_tdi( jtag_tdi ),
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.jtag_clk( jtag_tck ),
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.jtag_reset_n( rstn ),
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.jtag_tms( jtag_tms )
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);
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tb_slave #(.DWIDTH(16),
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tb_slave #(.DWIDTH(16),
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.SINGLE_CYCLE(1'b1),
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.SINGLE_CYCLE(1'b1),
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.MAX_CHANNEL(MAX_CHANNEL))
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.MAX_CHANNEL(MAX_CHANNEL))
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tb_slave_regs(
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tb_slave_regs(
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// wishbone interface
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// wishbone interface
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Line 503... |
Line 484... |
sync_reset = 1'b0;
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sync_reset = 1'b0;
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channel_req = 0; //
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channel_req = 0; //
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|
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$display("\nstatus at time: %t done reset", $time);
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$display("\nstatus at time: %t done reset", $time);
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test_skipjack;
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test_inst_set;
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test_inst_set;
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test_debug_mode;
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test_debug_mode;
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test_debug_bit;
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test_debug_bit;
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Line 517... |
Line 500... |
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reg_irq;
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reg_irq;
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// host_ram;
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// host_ram;
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// test_skipjack;
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// End testing
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// End testing
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wrap_up;
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wrap_up;
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end
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end
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// Main JTAG Test Program
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initial
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begin
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$display("\nstatus at time: %t Testbench started", $time);
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// tms, tdi
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send_jtag_bit(1,0); // RUN/TEST/IDLE
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send_jtag_bit(0,1); // SEL DR
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send_jtag_bit(1,1); // SEL IR
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send_jtag_bit(1,1); // Capture IR
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send_jtag_bit(0,1); // Dead Bit?
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send_jtag_bit(0,1); // LSB
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send_jtag_bit(0,0); // Bit 1
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send_jtag_bit(0,1); // Bit 2
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send_jtag_bit(0,0); // Bit 3
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send_jtag_bit(1,1); // EXIT1 IR
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send_jtag_bit(1,1); // UPDATE IR
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send_jtag_bit(0,1); // RUN/TEST/IDLE
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send_jtag_bit(0,1); // RUN/TEST/IDLE
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end
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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// Test CHID Debug mode operation
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// Test CHID Debug mode operation
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task test_chid_debug;
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task test_chid_debug;
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begin
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begin
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test_num = test_num + 1;
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test_num = test_num + 1;
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Line 669... |
Line 629... |
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host.wb_read(1, XGATE_XGR3, q, WORD);
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host.wb_read(1, XGATE_XGR3, q, WORD);
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data_xgmctl = XGMCTL_XGSSM | XGMCTL_XGSS;
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data_xgmctl = XGMCTL_XGSSM | XGMCTL_XGSS;
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qq = q;
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qq = q;
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// The Xgate test program is in an infinate loop incrementing R3
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// The Xgate test program is in an infinite loop incrementing R3
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while (qq == q) // Look for change in R3 register
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while (qq == q) // Look for change in R3 register
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begin
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begin
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host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD); // Do a Single Step
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host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD); // Do a Single Step
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repeat(XGATE_SS_DELAY) @(posedge mstr_test_clk);
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repeat(XGATE_SS_DELAY) @(posedge mstr_test_clk);
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host.wb_read(1, XGATE_XGR3, q, WORD);
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host.wb_read(1, XGATE_XGR3, q, WORD);
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Line 869... |
Line 829... |
read_ram_cmp(16'h0068,16'h2fcc);
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read_ram_cmp(16'h0068,16'h2fcc);
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read_ram_cmp(16'h0022,16'hccxx);
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read_ram_cmp(16'h0022,16'hccxx);
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read_ram_cmp(16'h0026,16'hxx99);
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read_ram_cmp(16'h0026,16'hxx99);
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read_ram_cmp(16'h0052,16'hxx66);
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read_ram_cmp(16'h0052,16'hxx66);
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read_ram_cmp(16'h0058,16'h99xx);
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read_ram_cmp(16'h0058,16'h99xx);
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read_ram_cmp(16'h0080, 16'h9966);
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read_ram_cmp(16'h0086, 16'h7533);
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data_xgmctl = 16'hff00;
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data_xgmctl = 16'hff00;
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host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD); // Disable XGATE
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host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD); // Disable XGATE
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|
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end
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end
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endtask
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endtask
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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// Test SKIPJACK Application Program
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// Test instruction set
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task test_skipjack;
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task test_skipjack;
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begin
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begin
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$readmemh("../../../bench/verilog/skipjack.v", p_ram.ram_8);
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$readmemh("../../../bench/verilog/skipjack.v", p_ram.ram_8);
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test_num = test_num + 1;
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test_num = test_num + 1;
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$display("\nTEST #%d Starts at vector=%d, test_skipjack", test_num, vector);
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$display("\nTEST #%d Starts at vector=%d, test_skipjack", test_num, vector);
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Line 941... |
Line 903... |
host.wb_cmp(0, XGATE_XGR4, 16'h0000, WORD); // verify reset
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host.wb_cmp(0, XGATE_XGR4, 16'h0000, WORD); // verify reset
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host.wb_cmp(0, XGATE_XGR5, 16'h0000, WORD); // verify reset
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host.wb_cmp(0, XGATE_XGR5, 16'h0000, WORD); // verify reset
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host.wb_cmp(0, XGATE_XGR6, 16'h0000, WORD); // verify reset
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host.wb_cmp(0, XGATE_XGR6, 16'h0000, WORD); // verify reset
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host.wb_cmp(0, XGATE_XGR7, 16'h0000, WORD); // verify reset
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host.wb_cmp(0, XGATE_XGR7, 16'h0000, WORD); // verify reset
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|
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/*
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|
parameter XGMCTL_XGDBGM = 15'h2000;
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parameter XGMCTL_XGSSM = 15'h1000;
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parameter XGMCTL_XGBRKIEM = 15'h0400;
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parameter XGMCTL_XGSWEIFM = 15'h0200;
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parameter XGMCTL_XGIEM = 15'h0100;
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parameter XGMCTL_XGDBG = 15'h0020;
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parameter XGMCTL_XGSS = 15'h0010;
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parameter XGMCTL_XGBRKIE = 15'h0004;
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parameter XGMCTL_XGSWEIF = 15'h0002;
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parameter XGMCTL_XGIE = 15'h0001;
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|
*/
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|
// Test bits in the Xgate Control Register (XGMCTL)
|
// Test bits in the Xgate Control Register (XGMCTL)
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data_xgmctl = XGMCTL_XGEM | XGMCTL_XGFRZM | XGMCTL_XGFACTM | XGMCTL_XGFRZ | XGMCTL_XGFACT | XGMCTL_XGE;
|
data_xgmctl = XGMCTL_XGEM | XGMCTL_XGFRZM | XGMCTL_XGFACTM | XGMCTL_XGFRZ | XGMCTL_XGFACT | XGMCTL_XGE;
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host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD); //
|
host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD); //
|
data_xgmctl = XGMCTL_XGFRZ | XGMCTL_XGFACT | XGMCTL_XGE;
|
data_xgmctl = XGMCTL_XGFRZ | XGMCTL_XGFACT | XGMCTL_XGE;
|
host.wb_cmp( 0, XGATE_XGMCTL, data_xgmctl, WORD);
|
host.wb_cmp( 0, XGATE_XGMCTL, data_xgmctl, WORD);
|
Line 1155... |
Line 1104... |
host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD); // Enable XGATE
|
host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD); // Enable XGATE
|
repeat(XGATE_ACCESS_DELAY+2) @(posedge mstr_test_clk);
|
repeat(XGATE_ACCESS_DELAY+2) @(posedge mstr_test_clk);
|
channel_req[3:1] = 3'b111; //
|
channel_req[3:1] = 3'b111; //
|
|
|
q = 0;
|
q = 0;
|
// The Xgate test program is in an infinate loop for the test bench semaphore register to be changed
|
// The Xgate test program is in an infinite loop for the test bench semaphore register to be changed
|
while (q == 0) // Look for change in test bench semapore register
|
while (q == 0) // Look for change in test bench semapore register
|
begin
|
begin
|
host.wb_read(1, TB_SEMPHORE, q, WORD);
|
host.wb_read(1, TB_SEMPHORE, q, WORD);
|
end
|
end
|
|
|
Line 1177... |
Line 1126... |
// host.wb_cmp(0, XGATE_XGIF_0, 16'h0002, WORD); // Verify Xgate interrupt status bit set
|
// host.wb_cmp(0, XGATE_XGIF_0, 16'h0002, WORD); // Verify Xgate interrupt status bit set
|
host.wb_write(1, XGATE_XGIF_0, 16'h0002, WORD); // Clear Interrupt Flag from Xgate
|
host.wb_write(1, XGATE_XGIF_0, 16'h0002, WORD); // Clear Interrupt Flag from Xgate
|
// host.wb_cmp(0, XGATE_XGIF_0, 16'h0000, WORD); // Verify flag cleared
|
// host.wb_cmp(0, XGATE_XGIF_0, 16'h0000, WORD); // Verify flag cleared
|
|
|
q = 0;
|
q = 0;
|
// The Xgate test program is in an infinate loop for the test bench semaphore register to be changed
|
// The Xgate test program is in an infinite loop for the test bench semaphore register to be changed
|
while (q == 0) // Look for change in test bench semapore register
|
while (q == 0) // Look for change in test bench semapore register
|
begin
|
begin
|
host.wb_read(1, TB_SEMPHORE, q, WORD);
|
host.wb_read(1, TB_SEMPHORE, q, WORD);
|
end
|
end
|
|
|
Line 1199... |
Line 1148... |
// host.wb_cmp(0, XGATE_XGIF_0, 16'h0002, WORD); // Verify Xgate interrupt status bit set
|
// host.wb_cmp(0, XGATE_XGIF_0, 16'h0002, WORD); // Verify Xgate interrupt status bit set
|
host.wb_write(1, XGATE_XGIF_0, 16'h0004, WORD); // Clear Interrupt Flag from Xgate
|
host.wb_write(1, XGATE_XGIF_0, 16'h0004, WORD); // Clear Interrupt Flag from Xgate
|
// host.wb_cmp(0, XGATE_XGIF_0, 16'h0000, WORD); // Verify flag cleared
|
// host.wb_cmp(0, XGATE_XGIF_0, 16'h0000, WORD); // Verify flag cleared
|
|
|
q = 0;
|
q = 0;
|
// The Xgate test program is in an infinate loop for the test bench semaphore register to be changed
|
// The Xgate test program is in an infinite loop for the test bench semaphore register to be changed
|
while (q == 0) // Look for change in test bench semapore register
|
while (q == 0) // Look for change in test bench semapore register
|
begin
|
begin
|
host.wb_read(1, TB_SEMPHORE, q, WORD);
|
host.wb_read(1, TB_SEMPHORE, q, WORD);
|
end
|
end
|
|
|
Line 1383... |
Line 1332... |
$finish;
|
$finish;
|
end
|
end
|
endtask
|
endtask
|
|
|
////////////////////////////////////////////////////////////////////////////////
|
////////////////////////////////////////////////////////////////////////////////
|
task send_jtag_bit;
|
|
input tms_val;
|
|
input tdi_val;
|
|
begin
|
|
jtag_tck = 0;
|
|
repeat(JTAG_PERIOD) @(posedge mstr_test_clk);
|
|
jtag_tck = 1;
|
|
#1;
|
|
jtag_tms = tms_val;
|
|
jtag_tdi = tdi_val;
|
|
repeat(JTAG_PERIOD) @(posedge mstr_test_clk);
|
|
jtag_tck = 0;
|
|
end
|
|
endtask
|
|
|
|
////////////////////////////////////////////////////////////////////////////////
|
|
function [15:0] four_2_16;
|
function [15:0] four_2_16;
|
input [3:0] vector;
|
input [3:0] vector;
|
begin
|
begin
|
case (vector)
|
case (vector)
|
4'h0 : four_2_16 = 16'b0000_0000_0000_0001;
|
4'h0 : four_2_16 = 16'b0000_0000_0000_0001;
|
Line 1892... |
Line 1825... |
break_addr_3 = 0;
|
break_addr_3 = 0;
|
break_addr_4 = 0;
|
break_addr_4 = 0;
|
break_addr_5 = 0;
|
break_addr_5 = 0;
|
break_addr_6 = 0;
|
break_addr_6 = 0;
|
break_addr_7 = 0;
|
break_addr_7 = 0;
|
repeat(4) @(posedge risc_clk); // Note: !! This should come after code load
|
repeat(4) @(posedge risc_clk);
|
break_addr_0 = {p_ram.ram_8[BREAK_CAPT_0], p_ram.ram_8[BREAK_CAPT_0+1]};
|
break_addr_0 = {p_ram.ram_8[BREAK_CAPT_0], p_ram.ram_8[BREAK_CAPT_0+1]};
|
break_addr_1 = {p_ram.ram_8[BREAK_CAPT_1], p_ram.ram_8[BREAK_CAPT_1+1]};
|
break_addr_1 = {p_ram.ram_8[BREAK_CAPT_1], p_ram.ram_8[BREAK_CAPT_1+1]};
|
break_addr_2 = {p_ram.ram_8[BREAK_CAPT_2], p_ram.ram_8[BREAK_CAPT_2+1]};
|
break_addr_2 = {p_ram.ram_8[BREAK_CAPT_2], p_ram.ram_8[BREAK_CAPT_2+1]};
|
break_addr_3 = {p_ram.ram_8[BREAK_CAPT_3], p_ram.ram_8[BREAK_CAPT_3+1]};
|
break_addr_3 = {p_ram.ram_8[BREAK_CAPT_3], p_ram.ram_8[BREAK_CAPT_3+1]};
|
break_addr_4 = {p_ram.ram_8[BREAK_CAPT_4], p_ram.ram_8[BREAK_CAPT_4+1]};
|
break_addr_4 = {p_ram.ram_8[BREAK_CAPT_4], p_ram.ram_8[BREAK_CAPT_4+1]};
|