OpenCores
URL https://opencores.org/ocsvn/xgate/xgate/trunk

Subversion Repositories xgate

[/] [xgate/] [trunk/] [bench/] [verilog/] [tst_bench_top.v] - Diff between revs 89 and 94

Go to most recent revision | Show entire file | Details | Blame | View Log

Rev 89 Rev 94
Line 43... Line 43... 
 
 
 
 
module tst_bench_top();
 
module tst_bench_top();
 
 
 
 
 
  parameter MAX_CHANNEL   = 127;    // Max XGATE Interrupt Channel Number
 
  parameter MAX_CHANNEL   = 127;    // Max XGATE Interrupt Channel Number
 
  parameter STOP_ON_ERROR = 1'b0;
 
  parameter STOP_ON_ERROR = 1'b0;
 
  parameter MAX_VECTOR    = 12_000;
 
  parameter MAX_VECTOR    = 22_000;
 
 
 
 
 
  parameter L_BYTE = 2'b01;
 
  parameter L_BYTE = 2'b01;
 
  parameter H_BYTE = 2'b10;
 
  parameter H_BYTE = 2'b10;
 
  parameter WORD   = 2'b11;
 
  parameter WORD   = 2'b11;
 
 
 
 
 
 
 
  parameter TB_ADDR_WIDTH = 24;  // Testbench address bus width
 
 
 
  parameter TB_DATA_WIDTH = 16;
 
 
 
 
 
 
 
 
 
  // Name Address Locations
 
  // Name Address Locations
 
  parameter XGATE_BASE     = 24'h1000;
 
  parameter XGATE_BASE     = 24'h1000;
 
  parameter XGATE_XGMCTL   = XGATE_BASE + 6'h00;
 
  parameter XGATE_XGMCTL   = XGATE_BASE + 6'h00;
 
  parameter XGATE_XGCHID   = XGATE_BASE + 6'h02;
 
  parameter XGATE_XGCHID   = XGATE_BASE + 6'h02;
Line 97... Line 100... 
  parameter XGMCTL_XGFACT   = 15'h0008;
 
  parameter XGMCTL_XGFACT   = 15'h0008;
 
  parameter XGMCTL_XGBRKIE  = 15'h0004;
 
  parameter XGMCTL_XGBRKIE  = 15'h0004;
 
  parameter XGMCTL_XGSWEIF  = 15'h0002;
 
  parameter XGMCTL_XGSWEIF  = 15'h0002;
 
  parameter XGMCTL_XGIE     = 15'h0001;
 
  parameter XGMCTL_XGIE     = 15'h0001;
 
 
 
 
 
 
 
  // Define Address locations used by the testbench
 
  parameter CHECK_POINT     = 16'h8000;
 
  parameter CHECK_POINT     = 16'h8000;
 
  parameter CHANNEL_ACK     = CHECK_POINT + 2;
 
  parameter CHANNEL_ACK     = CHECK_POINT + 2;
 
  parameter CHANNEL_ERR     = CHECK_POINT + 4;
 
  parameter CHANNEL_ERR     = CHECK_POINT + 4;
 
  parameter DEBUG_CNTRL     = CHECK_POINT + 6;
 
  parameter DEBUG_CNTRL     = CHECK_POINT + 6;
 
  parameter TB_SEMPHORE     = CHECK_POINT + 10;
 
  parameter TB_SEMPHORE     = CHECK_POINT + 10;
Line 149... Line 153... 
 
 
 
 
  reg  [15:0] q, qq;
 
  reg  [15:0] q, qq;
 
 
 
 
 
  reg       rstn;
 
  reg       rstn;
 
  reg       sync_reset;
 
  reg       sync_reset;
 
  reg       por_reset_b;
 
 
 
  reg       scantestmode;
 
  reg       scantestmode;
 
 
 
 
 
  reg  [MAX_CHANNEL:1] channel_req;  // XGATE Interrupt inputs
 
  reg  [MAX_CHANNEL:1] channel_req;  // XGATE Interrupt inputs
 
  wire [MAX_CHANNEL:1] xgif;         // XGATE Interrupt outputs
 
  wire [MAX_CHANNEL:1] xgif;         // XGATE Interrupt outputs
 
  wire         [  7:0] xgswt;        // XGATE Software Trigger outputs
 
  wire         [  7:0] xgswt;        // XGATE Software Trigger outputs
Line 226... Line 229... 
  initial
 
  initial
 
    begin
 
    begin
 
      mstr_test_clk = 0;
 
      mstr_test_clk = 0;
 
      vector        = 0;
 
      vector        = 0;
 
      test_num      = 0;
 
      test_num      = 0;
 
      por_reset_b   = 0;
 
 
 
      scantestmode  = 0;
 
      scantestmode  = 0;
 
      error_count   = 0;
 
      error_count   = 0;
 
      mem_wait_state_enable = 0;
 
      mem_wait_state_enable = 0;
 
      // channel_req = 0;
 
      // channel_req = 0;
 
 
 
 
Line 304... Line 306... 
    .stb( mstr_test_clk ),
 
    .stb( mstr_test_clk ),
 
    .sel( sys_sel )
 
    .sel( sys_sel )
 
  );
 
  );
 
 
 
 
 
  // hookup wishbone master model
 
  // hookup wishbone master model
 
  wb_master_model #(.dwidth(16), .awidth(24))
 
  wb_master_model #(.dwidth(TB_DATA_WIDTH), .awidth(TB_ADDR_WIDTH))
 
    host(
 
    host(
 
    // Outputs
 
    // Outputs
 
    .cyc( host_cyc ),
 
    .cyc( host_cyc ),
 
    .stb( host_stb ),
 
    .stb( host_stb ),
 
    .we( host_we ),
 
    .we( host_we ),
Line 322... Line 324... 
    .rst( rstn ),
 
    .rst( rstn ),
 
    .err( 1'b0 ),
 
    .err( 1'b0 ),
 
    .rty( 1'b0 )
 
    .rty( 1'b0 )
 
  );
 
  );
 
 
 
 
 
  bus_arbitration  #(.dwidth(16),
 
  bus_arbitration  #(.dwidth(TB_DATA_WIDTH),
 
                     .awidth(24),
 
                     .awidth(TB_ADDR_WIDTH),
 
                     .ram_base(0),
 
                     .ram_base(0),
 
                     .ram_size(17'h10000),
 
                     .ram_size(17'h10000),
 
                     .slv1_base(XGATE_BASE),
 
                     .slv1_base(XGATE_BASE),
 
                     .slv1_size(128),
 
                     .slv1_size(128),
 
                     .slv2_base(CHECK_POINT),
 
                     .slv2_base(CHECK_POINT),
Line 384... Line 386... 
               .WB_RD_DEFAULT(1'b0),
 
               .WB_RD_DEFAULT(1'b0),
 
               .MAX_CHANNEL(MAX_CHANNEL))    // Max XGATE Interrupt Channel Number
 
               .MAX_CHANNEL(MAX_CHANNEL))    // Max XGATE Interrupt Channel Number
 
    xgate(
 
    xgate(
 
    // Wishbone slave interface
 
    // Wishbone slave interface
 
    .wbs_clk_i( mstr_test_clk ),
 
    .wbs_clk_i( mstr_test_clk ),
 
    .wbs_rst_i( 1'b0 ),       // sync_reset
 
    .wbs_rst_i( sync_reset ),       // sync_reset
 
    .arst_i( rstn ),          // async resetn
 
    .arst_i( rstn ),          // async resetn
 
    .wbs_adr_i( sys_adr[6:1] ),
 
    .wbs_adr_i( sys_adr[6:1] ),
 
    .wbs_dat_i( sys_dout ),
 
    .wbs_dat_i( sys_dout ),
 
    .wbs_dat_o( xgate_s_dout ),
 
    .wbs_dat_o( xgate_s_dout ),
 
    .wbs_we_i( sys_we ),
 
    .wbs_we_i( sys_we ),
Line 468... Line 470... 
initial
 
initial
 
  begin
 
  begin
 
    $display("\nstatus at time: %t Testbench started", $time);
 
    $display("\nstatus at time: %t Testbench started", $time);
 
 
 
 
 
    // reset system
 
    // reset system
 
    rstn = 1'b1;        // negate reset
 
    rstn        <= 1'b0; // negate reset
 
    channel_req = 1;    //
 
    channel_req <= 1;    //
 
    repeat(1) @(posedge mstr_test_clk);
 
    sync_reset  <= 1'b0; // Don't do sync reset
 
    sync_reset = 1'b1;  // Make the sync reset 1 clock cycle long
 
 
 
    #2;                 // move the async reset away from the clock edge
 
 
 
    rstn = 1'b0;        // assert async reset
 
 
 
    #5;                 // Keep the async reset pulse with less than a clock cycle
 
    #5;                 // Keep the async reset pulse with less than a clock cycle
 
    rstn = 1'b1;        // negate async reset
 
    rstn = 1'b1;        // negate async reset
 
    por_reset_b = 1'b1;
 
 
 
    channel_req = 0;    //
 
    channel_req = 0;    //
 
    repeat(1) @(posedge mstr_test_clk);
 
    repeat(1) @(posedge mstr_test_clk);
 
    sync_reset = 1'b0;
 
 
 
    channel_req = 0;    //
 
 
 
 
 
 
 
    $display("\nstatus at time: %t done reset", $time);
 
    $display("\nstatus at time: %t done reset", $time);
 
 
 
 
 
    test_skipjack;
 
    test_skipjack;
 
 
 
 
Line 498... Line 494... 
 
 
 
 
    reg_test_16;
 
    reg_test_16;
 
 
 
 
 
    reg_irq;
 
    reg_irq;
 
 
 
 
 
 
 
    sync_reset_test;
 
 
 
 
 
    // host_ram;
 
    // host_ram;
 
 
 
 
 
    // End testing
 
    // End testing
 
    wrap_up;
 
    wrap_up;
 
  end
 
  end
Line 764... Line 762... 
    repeat(1) @(posedge mstr_test_clk);
 
    repeat(1) @(posedge mstr_test_clk);
 
 
 
 
 
    // Enable interrupts to RISC
 
    // Enable interrupts to RISC
 
    host.wb_write(0, IRQ_BYPS_0,  16'h0000, WORD);
 
    host.wb_write(0, IRQ_BYPS_0,  16'h0000, WORD);
 
 
 
 
 
 
 
    // Test Shift instructions
 
    activate_thread_sw(1);
 
    activate_thread_sw(1);
 
    wait_irq_set(1);
 
    wait_irq_set(1);
 
    host.wb_write(1, XGATE_XGIF_0, 16'h0002, WORD);
 
    host.wb_write(1, XGATE_XGIF_0, 16'h0002, WORD);
 
 
 
 
 
 
 
    // Test Logical Byte wide instructions
 
    activate_thread_sw(2);
 
    activate_thread_sw(2);
 
    wait_irq_set(2);
 
    wait_irq_set(2);
 
    host.wb_write(1, XGATE_XGIF_0, 16'h0004, WORD);
 
    host.wb_write(1, XGATE_XGIF_0, 16'h0004, WORD);
 
 
 
 
 
 
 
    // Test Logical Word Wide instructions
 
    activate_thread_sw(3);
 
    activate_thread_sw(3);
 
    wait_irq_set(3);
 
    wait_irq_set(3);
 
    host.wb_write(1, XGATE_XGIF_0, 16'h0008, WORD);
 
    host.wb_write(1, XGATE_XGIF_0, 16'h0008, WORD);
 
 
 
 
 
 
 
    // Test Bit Field instructions
 
    activate_thread_sw(4);
 
    activate_thread_sw(4);
 
    wait_irq_set(4);
 
    wait_irq_set(4);
 
    host.wb_write(1, XGATE_XGIF_0, 16'h0010, WORD);
 
    host.wb_write(1, XGATE_XGIF_0, 16'h0010, WORD);
 
 
 
 
 
 
 
    // Test Branch instructions
 
    activate_thread_sw(5);
 
    activate_thread_sw(5);
 
    wait_irq_set(5);
 
    wait_irq_set(5);
 
    host.wb_write(1, XGATE_XGIF_0, 16'h0020, WORD);
 
    host.wb_write(1, XGATE_XGIF_0, 16'h0020, WORD);
 
 
 
 
 
 
 
    // Test Subroutine Call and return instructions
 
    activate_thread_sw(6);
 
    activate_thread_sw(6);
 
    wait_irq_set(6);
 
    wait_irq_set(6);
 
    host.wb_write(1, XGATE_XGIF_0, 16'h0040, WORD);
 
    host.wb_write(1, XGATE_XGIF_0, 16'h0040, WORD);
 
 
 
 
 
 
 
    // Test 16 bit Addition and Substract instructions
 
    activate_thread_sw(7);
 
    activate_thread_sw(7);
 
    wait_irq_set(7);
 
    wait_irq_set(7);
 
    host.wb_write(1, XGATE_XGIF_0, 16'h0080, WORD);
 
    host.wb_write(1, XGATE_XGIF_0, 16'h0080, WORD);
 
 
 
 
 
 
 
    // Test 8 bit Addition and Substract instructions
 
    activate_thread_sw(8);
 
    activate_thread_sw(8);
 
    wait_irq_set(8);
 
    wait_irq_set(8);
 
    host.wb_write(1, XGATE_XGIF_0, 16'h0100, WORD);
 
    host.wb_write(1, XGATE_XGIF_0, 16'h0100, WORD);
 
 
 
 
 
 
 
    // Test Load and Store instructions
 
    activate_thread_sw(9);
 
    activate_thread_sw(9);
 
    wait_irq_set(9);
 
    wait_irq_set(9);
 
    host.wb_write(1, XGATE_XGIF_0, 16'h0200, WORD);
 
    host.wb_write(1, XGATE_XGIF_0, 16'h0200, WORD);
 
 
 
 
 
 
 
    // Test Semaphore instructions
 
    host.wb_write(1, XGATE_XGSEM, 16'h5050, WORD);
 
    host.wb_write(1, XGATE_XGSEM, 16'h5050, WORD);
 
    host.wb_cmp(0, XGATE_XGSEM,    16'h0050, WORD);   //
 
    host.wb_cmp(0, XGATE_XGSEM,    16'h0050, WORD);   //
 
    activate_thread_sw(10);
 
    activate_thread_sw(10);
 
    wait_irq_set(10);
 
    wait_irq_set(10);
 
    host.wb_write(1, XGATE_XGIF_0, 16'h0400, WORD);
 
    host.wb_write(1, XGATE_XGIF_0, 16'h0400, WORD);
Line 839... Line 847... 
 
 
 
 
  end
 
  end
 
endtask
 
endtask
 
 
 
 
 
////////////////////////////////////////////////////////////////////////////////
 
////////////////////////////////////////////////////////////////////////////////
 
// Test instruction set
 
// Test skipjack encription - test subset of instruction set on a real problem
 
task test_skipjack;
 
task test_skipjack;
 
  begin
 
  begin
 
    $readmemh("../../../bench/verilog/skipjack.v", p_ram.ram_8);
 
    $readmemh("../../../bench/verilog/skipjack.v", p_ram.ram_8);
 
    test_num = test_num + 1;
 
    test_num = test_num + 1;
 
    $display("\nTEST #%d Starts at vector=%d, test_skipjack", test_num, vector);
 
    $display("\nTEST #%d Starts at vector=%d, test_skipjack", test_num, vector);
Line 1059... Line 1067... 
endtask
 
endtask
 
 
 
 
 
////////////////////////////////////////////////////////////////////////////////
 
////////////////////////////////////////////////////////////////////////////////
 
// check irq register bits - reset, read/write
 
// check irq register bits - reset, read/write
 
task reg_irq;
 
task reg_irq;
 
 
 
  integer i, j, k;
 
 
 
  reg [15:0] irq_clear;
 
 
 
  reg [TB_ADDR_WIDTH-1:0] irq_ack_addr; // Address to clear irq request
 
  begin
 
  begin
 
    test_num = test_num + 1;
 
    test_num = test_num + 1;
 
    $display("\nTEST #%d Starts at vector=%d, reg_irq", test_num, vector);
 
    $display("\nTEST #%d Starts at vector=%d, reg_irq", test_num, vector);
 
    $readmemh("../../../bench/verilog/irq_test.v", p_ram.ram_8);
 
    $readmemh("../../../bench/verilog/irq_test.v", p_ram.ram_8);
 
 
 
 
Line 1097... Line 1108... 
    repeat(4) @(posedge mstr_test_clk);
 
    repeat(4) @(posedge mstr_test_clk);
 
    host.wb_cmp(0, CHANNEL_XGIRQ_1,    16'h0000, WORD);
 
    host.wb_cmp(0, CHANNEL_XGIRQ_1,    16'h0000, WORD);
 
 
 
 
 
    host.wb_write(0, TB_SEMPHORE,  16'h0000, WORD);
 
    host.wb_write(0, TB_SEMPHORE,  16'h0000, WORD);
 
    host.wb_write(0, IRQ_BYPS_0,  16'h0000, WORD);
 
    host.wb_write(0, IRQ_BYPS_0,  16'h0000, WORD);
 
    host.wb_write(0, IRQ_BYPS_0,  16'h0000, WORD);
 
    host.wb_write(0, IRQ_BYPS_1,  16'h0000, WORD);
 
 
 
    host.wb_write(0, IRQ_BYPS_2,  16'h0000, WORD);
 
 
 
    host.wb_write(0, IRQ_BYPS_3,  16'h0000, WORD);
 
 
 
    host.wb_write(0, IRQ_BYPS_4,  16'h0000, WORD);
 
 
 
    host.wb_write(0, IRQ_BYPS_5,  16'h0000, WORD);
 
 
 
    host.wb_write(0, IRQ_BYPS_6,  16'h0000, WORD);
 
 
 
    host.wb_write(0, IRQ_BYPS_7,  16'h0000, WORD);
 
    data_xgmctl = XGMCTL_XGEM | XGMCTL_XGE;
 
    data_xgmctl = XGMCTL_XGEM | XGMCTL_XGE;
 
    host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD);   // Enable XGATE
 
    host.wb_write(0, XGATE_XGMCTL, data_xgmctl, WORD);   // Enable XGATE
 
    repeat(XGATE_ACCESS_DELAY+2) @(posedge mstr_test_clk);
 
    repeat(XGATE_ACCESS_DELAY+2) @(posedge mstr_test_clk);
 
    channel_req[3:1] = 3'b111; //
 
 
 
 
 
 
 
 
 
    //channel_req[8:1] = 8'b1_1111_111; //  Activate the interrupt inputs
 
 
 
    channel_req = {MAX_CHANNEL{1'b1}}; //  Activate the interrupt inputs
 
 
 
 
 
 
 
    for (i = 1; i <= MAX_CHANNEL; i = i + 1)
 
 
 
    begin
 
 
 
      j = i % 16;
 
 
 
      k = i / 16;
 
 
 
      irq_ack_addr = XGATE_XGIF_0 - (2 * k);
 
 
 
      $display("Testing interrupt %d.", i);
 
    q = 0;
 
    q = 0;
 
    // The Xgate test program is in an infinite loop for the test bench semaphore register to be changed
 
      // The Xgate test program is in an infinite loop looking for the test bench semaphore register to be changed
 
    while (q == 0)  // Look for change in test bench semapore register
 
    while (q == 0)  // Look for change in test bench semapore register
 
      begin
 
      begin
 
        host.wb_read(1, TB_SEMPHORE, q, WORD);
 
        host.wb_read(1, TB_SEMPHORE, q, WORD);
 
      end
 
      end
 
 
 
 
 
    if (q != 1)
 
      if (q != i)
 
      begin
 
      begin
 
 
 
          error_count = error_count + 1;
 
        $display("IRQ test failure, Wrong interrupt being processed! Interrupt=%d, vector=%d", q, vector);
 
        $display("IRQ test failure, Wrong interrupt being processed! Interrupt=%d, vector=%d", q, vector);
 
      end
 
      end
 
 
 
 
 
    channel_req[1] = 1'b0; //
 
      channel_req[i] = 1'b0; //  Clear the active interrupt input
 
    repeat(XGATE_ACCESS_DELAY+2) @(posedge mstr_test_clk);
 
    repeat(XGATE_ACCESS_DELAY+2) @(posedge mstr_test_clk);
 
    host.wb_write(0, TB_SEMPHORE,  16'h0000, WORD);
 
    host.wb_write(0, TB_SEMPHORE,  16'h0000, WORD);
 
    repeat(XGATE_ACCESS_DELAY+2) @(posedge mstr_test_clk);
 
    repeat(XGATE_ACCESS_DELAY+2) @(posedge mstr_test_clk);
 
 
 
 
 
//    host.wb_cmp(0, CHANNEL_XGIRQ_0, 16'h0002, WORD);  // Verify Xgate output interrupt flag set
 
      irq_clear = 16'h0001 << j;
 
//    host.wb_cmp(0, XGATE_XGIF_0,    16'h0002, WORD);  // Verify Xgate interrupt status bit set
 
      // host.wb_cmp(0, CHANNEL_XGIRQ_0, irq_clear, WORD);  // Verify Xgate output interrupt flag set
 
    host.wb_write(1, XGATE_XGIF_0, 16'h0002, WORD);  // Clear Interrupt Flag from Xgate
 
      // host.wb_cmp(0, XGATE_XGIF_0,    irq_clear, WORD);  // Verify Xgate interrupt status bit set
 
 
 
      host.wb_write(1, irq_ack_addr, irq_clear, WORD);  // Clear Interrupt Flag from Xgate
 
//    host.wb_cmp(0, XGATE_XGIF_0,    16'h0000, WORD);  // Verify flag cleared
 
//    host.wb_cmp(0, XGATE_XGIF_0,    16'h0000, WORD);  // Verify flag cleared
 
 
 
 
 
    q = 0;
 
 
 
    // The Xgate test program is in an infinite loop for the test bench semaphore register to be changed
 
 
 
    while (q == 0)  // Look for change in test bench semapore register
 
 
 
      begin
 
 
 
        host.wb_read(1, TB_SEMPHORE, q, WORD);
 
 
 
      end
 
      end
 
 
 
 
 
    if (q != 2)
 
 
 
      begin
 
 
 
        $display("IRQ test failure, Wrong interrupt being processed! Interrupt=%d, vector=%d", q, vector);
 
 
 
      end
 
      end
 
 
 
endtask  // reg_irq
 
 
 
 
 
    channel_req[2] = 1'b0; //
 
 
 
    repeat(XGATE_ACCESS_DELAY+2) @(posedge mstr_test_clk);
 
 
 
    host.wb_write(0, TB_SEMPHORE,  16'h0000, WORD);
 
 
 
    repeat(XGATE_ACCESS_DELAY+2) @(posedge mstr_test_clk);
 
 
 
 
 
 
 
//    host.wb_cmp(0, CHANNEL_XGIRQ_0, 16'h0002, WORD);  // Verify Xgate output interrupt flag set
 
 
 
//    host.wb_cmp(0, XGATE_XGIF_0,    16'h0002, WORD);  // Verify Xgate interrupt status bit set
 
 
 
    host.wb_write(1, XGATE_XGIF_0, 16'h0004, WORD);  // Clear Interrupt Flag from Xgate
 
 
 
//    host.wb_cmp(0, XGATE_XGIF_0,    16'h0000, WORD);  // Verify flag cleared
 
 
 
 
 
 
 
    q = 0;
 
////////////////////////////////////////////////////////////////////////////////
 
    // The Xgate test program is in an infinite loop for the test bench semaphore register to be changed
 
task sync_reset_test;  // reset system
 
    while (q == 0)  // Look for change in test bench semapore register
 
 
 
      begin
 
      begin
 
        host.wb_read(1, TB_SEMPHORE, q, WORD);
 
    test_num = test_num + 1;
 
      end
 
    $display("\nTEST #%d Starts at vector=%d, reg_irq", test_num, vector);
 
 
 
 
 
    if (q != 3)
 
    // Write some registers so a change in state can be verified after reset
 
      begin
 
    host.wb_write(1, XGATE_XGVBR, 16'h01ff, WORD);  //
 
        $display("IRQ test failure, Wrong interrupt being processed! Interrupt=%d, vector=%d", q, vector);
 
    host.wb_write(0, IRQ_BYPS_0,  16'h0000, WORD);
 
      end
 
 
 
 
 
 
 
    channel_req[3] = 1'b0; //
 
    repeat(1) @(posedge mstr_test_clk);
 
    repeat(XGATE_ACCESS_DELAY+2) @(posedge mstr_test_clk);
 
    sync_reset  <= 1'b1; // 
    host.wb_write(0, TB_SEMPHORE,  16'h0000, WORD);
 
    repeat(1) @(posedge mstr_test_clk);
 
    repeat(XGATE_ACCESS_DELAY+2) @(posedge mstr_test_clk);
 
    sync_reset  <= 1'b0;
 
 
 
 
 
//    host.wb_cmp(0, CHANNEL_XGIRQ_0, 16'h0002, WORD);  // Verify Xgate output interrupt flag set
 
    host.wb_cmp(0, XGATE_XGVBR,    16'hfe00, WORD); // verify reset
 
//    host.wb_cmp(0, XGATE_XGIF_0,    16'h0002, WORD);  // Verify Xgate interrupt status bit set
 
    host.wb_cmp(0, IRQ_BYPS_0,     16'hFFFE, WORD); // verify reset
 
    host.wb_write(1, XGATE_XGIF_0, 16'h0008, WORD);  // Clear Interrupt Flag from Xgate
 
 
 
//    host.wb_cmp(0, XGATE_XGIF_0,    16'h0000, WORD);  // Verify flag cleared
 
 
 
 
 
 
 
  end
 
  end
 
endtask
 
endtask
 
 
 
 
 
 
 
 
 
////////////////////////////////////////////////////////////////////////////////
 
////////////////////////////////////////////////////////////////////////////////
 
 
 
// End Main test program tasks
 
 
 
// Begin test program helper tasks and functions
 
 
 
////////////////////////////////////////////////////////////////////////////////
 
 
 
 
 
 
 
////////////////////////////////////////////////////////////////////////////////
 
// check RAM Read/Write from host
 
// check RAM Read/Write from host
 
task host_ram;
 
task host_ram;
 
  begin
 
  begin
 
    test_num = test_num + 1;
 
    test_num = test_num + 1;
 
    $display("\nTEST #%d Starts at vector=%d, host_ram", test_num, vector);
 
    $display("\nTEST #%d Starts at vector=%d, host_ram", test_num, vector);
Line 1216... Line 1227... 
 
 
 
 
////////////////////////////////////////////////////////////////////////////////
 
////////////////////////////////////////////////////////////////////////////////
 
task system_reset;  // reset system
 
task system_reset;  // reset system
 
  begin
 
  begin
 
    repeat(1) @(posedge mstr_test_clk);
 
    repeat(1) @(posedge mstr_test_clk);
 
    sync_reset = 1'b1;  // Make the sync reset 1 clock cycle long
 
 
 
    #2;     // move the async reset away from the clock edge
 
    #2;     // move the async reset away from the clock edge
 
    rstn = 1'b0;    // assert async reset
 
    rstn = 1'b0;    // assert async reset
 
    #5;     // Keep the async reset pulse with less than a clock cycle
 
    #5;     // Keep the async reset pulse with less than a clock cycle
 
    rstn = 1'b1;    // negate async reset
 
    rstn = 1'b1;    // negate async reset
 
    repeat(1) @(posedge mstr_test_clk);
 
    repeat(1) @(posedge mstr_test_clk);
 
    sync_reset = 1'b0;
 
 
 
 
 
 
 
    $display("\nstatus: %t System Reset Task Done", $time);
 
    $display("\nstatus: %t System Reset Task Done", $time);
 
    test_num = test_num + 1;
 
    test_num = test_num + 1;
 
 
 
    channel_req = 0;  // Clear all the testbench inpterrupt inputs to the xgate
 
 
 
 
 
    repeat(2) @(posedge mstr_test_clk);
 
    repeat(2) @(posedge mstr_test_clk);
 
  end
 
  end
 
endtask
 
endtask
 
 
 
 
Line 1257... Line 1267... 
  end
 
  end
 
endtask
 
endtask
 
 
 
 
 
 
 
 
 
////////////////////////////////////////////////////////////////////////////////
 
////////////////////////////////////////////////////////////////////////////////
 
task clear_irq_flag;
 
 
 
  input [ 6:0] chan_val;
 
 
 
  begin
 
 
 
      $display("Clearing Channel interrupt flag #%d", chan_val);
 
 
 
      if (0 < chan_val < 16)
 
 
 
        host.wb_write(1, XGATE_XGIF_0, 16'hffff, WORD);
 
 
 
      if (15 < chan_val < 32)
 
 
 
        host.wb_write(1, XGATE_XGIF_1, 16'hffff, WORD);
 
 
 
      if (31 < chan_val < 48)
 
 
 
        host.wb_write(1, XGATE_XGIF_2, 16'hffff, WORD);
 
 
 
      if (47 < chan_val < 64)
 
 
 
        host.wb_write(1, XGATE_XGIF_3, 16'hffff, WORD);
 
 
 
      if (63 < chan_val < 80)
 
 
 
        host.wb_write(1, XGATE_XGIF_4, 16'hffff, WORD);
 
 
 
      if (79 < chan_val < 96)
 
 
 
        host.wb_write(1, XGATE_XGIF_5, 16'hffff, WORD);
 
 
 
      if (95 < chan_val < 112)
 
 
 
        host.wb_write(1, XGATE_XGIF_6, 16'hffff, WORD);
 
 
 
      if (111 < chan_val < 128)
 
 
 
        host.wb_write(1, XGATE_XGIF_7, 16'hffff, WORD);
 
 
 
 
 
 
 
      channel_req[chan_val] = 1'b0; //
 
 
 
      repeat(1) @(posedge mstr_test_clk);
 
 
 
   end
 
 
 
endtask
 
 
 
 
 
 
 
 
 
 
 
////////////////////////////////////////////////////////////////////////////////
 
 
 
task activate_thread_sw;
 
task activate_thread_sw;
 
  input [ 6:0] chan_val;
 
  input [ 6:0] chan_val;
 
  begin
 
  begin
 
      $display("Activating Software Thread - Channel #%d", chan_val);
 
      $display("Activating Software Thread - Channel #%d", chan_val);
 
 
 
 
Line 1356... Line 1338... 
      4'hf : four_2_16 = 16'b1000_0000_0000_0000;
 
      4'hf : four_2_16 = 16'b1000_0000_0000_0000;
 
    endcase
 
    endcase
 
  end
 
  end
 
endfunction
 
endfunction
 
 
 
 
 
 
 
 
 
endmodule  // tst_bench_top
 
endmodule  // tst_bench_top
 
 
 
 
 
////////////////////////////////////////////////////////////////////////////////
 
////////////////////////////////////////////////////////////////////////////////
 
////////////////////////////////////////////////////////////////////////////////
 
////////////////////////////////////////////////////////////////////////////////
 
////////////////////////////////////////////////////////////////////////////////
 
////////////////////////////////////////////////////////////////////////////////

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.