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[/] [xgate/] [trunk/] [bench/] [verilog/] [wb_master_model.v] - Diff between revs 2 and 20

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Line 49...	Line 49...
`//`	`//`
`include "timescale.v"	`include "timescale.v"

`module wb_master_model #(parameter dwidth = 32,`	`module wb_master_model #(parameter dwidth = 32,`
`parameter awidth = 32)`	`parameter awidth = 32)`
`(clk, rst, adr, din, dout, cyc, stb, we, sel, ack, err, rty);`	`(`
	`output reg cyc,`
	`output reg stb,`
`input clk, rst;`	`output reg we,`
`output [awidth -1:0] adr;`	`output reg [dwidth/8 -1:0] sel,`
`input [dwidth -1:0] din;`	`output reg [awidth -1:0] adr,`
`output [dwidth -1:0] dout;`	`output reg [dwidth -1:0] dout,`
`output cyc, stb;`	`input [dwidth -1:0] din,`
`output we;`	`input clk,`
`output [dwidth/8 -1:0] sel;`	`input ack,`
`input ack, err, rty;`	`input rst, // No Connect`
	`input err, // No Connect`
	`input rty // No Connect`
	`);`

`////////////////////////////////////////////////////////////////////`	`////////////////////////////////////////////////////////////////////`
`//`	`//`
`// Local Wires`	`// Local Wires`
`//`	`//`

`reg [awidth -1:0] adr;`
`reg [dwidth -1:0] dout;`
`reg cyc, stb;`
`reg we;`
`reg [dwidth/8 -1:0] sel;`

`reg [dwidth -1:0] q;`	`reg [dwidth -1:0] q;`

`event test_command_start;`	`event test_command_start;`
`event test_command_mid;`	`event test_command_mid;`
`event test_command_end;`	`event test_command_end;`

	`event cmp_error_detect;`

`////////////////////////////////////////////////////////////////////`	`////////////////////////////////////////////////////////////////////`
`//`	`//`
`// Memory Logic`	`// Memory Logic`
`//`	`//`

`initial`	`initial`
`begin`	`begin`
`//adr = 32'hxxxx_xxxx;`
`//adr = 0;`
`adr = {awidth{1'bx}};`	`adr = {awidth{1'bx}};`
`dout = {dwidth{1'bx}};`	`dout = {dwidth{1'bx}};`
`cyc = 1'b0;`	`cyc = 1'b0;`
`stb = 1'bx;`	`stb = 1'bx;`
`we = 1'hx;`	`we = 1'hx;`
`sel = {dwidth/8{1'bx}};`	`sel = {dwidth/8{1'bx}};`
`#1;`	`#1;`
`$display("\nINFO: WISHBONE MASTER MODEL INSTANTIATED (%m)");`	`$display("\nINFO: WISHBONE MASTER MODEL INSTANTIATED (%m)");`
`end`	`end`


`////////////////////////////////////////////////////////////////////`	`////////////////////////////////////////////////////////////////////`
`//`	`//`
`// Wishbone write cycle`	`// Wishbone write cycle`
`//`	`//`

Line 201...	Line 199...

`begin`	`begin`
`wb_read (delay, a, q);`	`wb_read (delay, a, q);`

`if (d_exp !== q)`	`if (d_exp !== q)`
	`begin`
	`-> cmp_error_detect;`
`$display("Data compare error at address %h. Received %h, expected %h at time %t", a, q, d_exp, $time);`	`$display("Data compare error at address %h. Received %h, expected %h at time %t", a, q, d_exp, $time);`
`end`	`end`
	`end`
`endtask`	`endtask`

`endmodule`	`endmodule`

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[/] [xgate/] [trunk/] [bench/] [verilog/] [wb_master_model.v] - Diff between revs 2 and 20