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[/] [xgate/] [trunk/] [bench/] [verilog/] [wb_master_model.v] - Diff between revs 27 and 35

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Rev 27 Rev 35
Line 106... Line 106...
        input   delay;
        input   delay;
        integer delay;
        integer delay;
 
 
        input   [awidth -1:0]   a;
        input   [awidth -1:0]   a;
        input   [dwidth -1:0]   d;
        input   [dwidth -1:0]   d;
 
        input   [dwidth/8 -1:0] s;
 
 
        begin
        begin
                -> test_command_start;
                -> test_command_start;
                // wait initial delay
                // wait initial delay
                repeat(delay) @(posedge clk);
                repeat(delay) @(posedge clk);
Line 119... Line 120...
                adr  = a;
                adr  = a;
                dout = d;
                dout = d;
                cyc  = 1'b1;
                cyc  = 1'b1;
                stb  = 1'b1;
                stb  = 1'b1;
                we   = 1'b1;
                we   = 1'b1;
                sel  = {dwidth/8{1'b1}};
                sel  = s;
                @(posedge clk);
                @(posedge clk);
                -> test_command_mid;
                -> test_command_mid;
 
 
                // wait for acknowledge from slave
                // wait for acknowledge from slave
                while(~ack)     @(posedge clk);
                while(~ack)     @(posedge clk);
Line 151... Line 152...
        input   delay;
        input   delay;
        integer delay;
        integer delay;
 
 
        input   [awidth -1:0]  a;
        input   [awidth -1:0]  a;
        output  [dwidth -1:0]  d;
        output  [dwidth -1:0]  d;
 
        input   [dwidth/8 -1:0] s;
 
 
        begin
        begin
 
 
                // wait initial delay
                // wait initial delay
                repeat(delay) @(posedge clk);
                repeat(delay) @(posedge clk);
Line 164... Line 166...
                adr  = a;
                adr  = a;
                dout = {dwidth{1'bx}};
                dout = {dwidth{1'bx}};
                cyc  = 1'b1;
                cyc  = 1'b1;
                stb  = 1'b1;
                stb  = 1'b1;
                we   = 1'b0;
                we   = 1'b0;
                sel  = {dwidth/8{1'b1}};
                sel  = s;
                @(posedge clk);
                @(posedge clk);
 
 
                // wait for acknowledge from slave
                // wait for acknowledge from slave
                while(~ack)     @(posedge clk);
                while(~ack)     @(posedge clk);
 
 
Line 194... Line 196...
        input   delay;
        input   delay;
        integer delay;
        integer delay;
 
 
        input [awidth -1:0]     a;
        input [awidth -1:0]     a;
        input [dwidth -1:0]     d_exp;
        input [dwidth -1:0]     d_exp;
 
        input [dwidth/8 -1:0] s;
 
 
        begin
        begin
                wb_read (delay, a, q);
                wb_read (delay, a, q, s);
 
 
                if (d_exp !== q)
                if (d_exp !== q)
                  begin
                  begin
                        -> cmp_error_detect;
                        -> cmp_error_detect;
                        $display("Data compare error at address %h. Received %h, expected %h at time %t", a, q, d_exp, $time);
                        $display("Data compare error at address %h. Received %h, expected %h at time %t", a, q, d_exp, $time);

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