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[/] [xgate/] [trunk/] [bench/] [verilog/] [wb_master_model.v] - Diff between revs 35 and 89
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| Rev 35 |
Rev 89 |
| Line 33... |
Line 33... |
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
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//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE ////
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//// POSSIBILITY OF SUCH DAMAGE. ////
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//// POSSIBILITY OF SUCH DAMAGE. ////
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//// ////
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//// ////
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///////////////////////////////////////////////////////////////////////
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///////////////////////////////////////////////////////////////////////
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// CVS Log
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//
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// $Id$
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//
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// $Date$
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// $Revision$
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// $Author$
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// $Locker$
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// $State$
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//
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// Change History:
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//
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//
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`include "timescale.v"
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`include "timescale.v"
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module wb_master_model #(parameter dwidth = 32,
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module wb_master_model #(parameter dwidth = 32,
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parameter awidth = 32)
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parameter awidth = 32)
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adr = {awidth{1'bx}};
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adr = {awidth{1'bx}};
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dout = {dwidth{1'bx}};
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dout = {dwidth{1'bx}};
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we = 1'hx;
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we = 1'hx;
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sel = {dwidth/8{1'bx}};
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sel = {dwidth/8{1'bx}};
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-> test_command_end;
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-> test_command_end;
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end
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end
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endtask
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endtask
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////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////
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//
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//
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// Wishbone read cycle
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// Wishbone read cycle
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input [awidth -1:0] a;
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input [awidth -1:0] a;
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output [dwidth -1:0] d;
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output [dwidth -1:0] d;
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input [dwidth/8 -1:0] s;
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input [dwidth/8 -1:0] s;
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begin
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begin
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// wait initial delay
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// wait initial delay
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repeat(delay) @(posedge clk);
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repeat(delay) @(posedge clk);
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// assert wishbone signals
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// assert wishbone signals
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#1;
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#1;
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stb = 1'bx;
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stb = 1'bx;
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adr = {awidth{1'bx}};
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adr = {awidth{1'bx}};
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dout = {dwidth{1'bx}};
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dout = {dwidth{1'bx}};
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we = 1'hx;
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we = 1'hx;
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sel = {dwidth/8{1'bx}};
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sel = {dwidth/8{1'bx}};
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end
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end
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endtask
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endtask
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////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////
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//
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//
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// Wishbone compare cycle (read data from location and compare with expected data)
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// Wishbone compare cycle (read data from location and compare with expected data)
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begin
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begin
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-> cmp_error_detect;
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-> cmp_error_detect;
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$display("Data compare error at address %h. Received %h, expected %h at time %t", a, q, d_exp, $time);
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$display("Data compare error at address %h. Received %h, expected %h at time %t", a, q, d_exp, $time);
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end
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end
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end
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end
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endtask
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endtask
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endmodule
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endmodule
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