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[/] [xgate/] [trunk/] [bench/] [verilog/] [wb_master_model.v] - Diff between revs 35 and 89

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Rev 35 Rev 89
Line 33... Line 33...
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE           ////
//// OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE           ////
//// POSSIBILITY OF SUCH DAMAGE.                                   ////
//// POSSIBILITY OF SUCH DAMAGE.                                   ////
////                                                               ////
////                                                               ////
///////////////////////////////////////////////////////////////////////
///////////////////////////////////////////////////////////////////////
 
 
//  CVS Log
 
//
 
//  $Id$
 
//
 
//  $Date$
 
//  $Revision$
 
//  $Author$
 
//  $Locker$
 
//  $State$
 
//
 
// Change History:
 
//
//
`include "timescale.v"
`include "timescale.v"
 
 
module wb_master_model  #(parameter dwidth = 32,
module wb_master_model  #(parameter dwidth = 32,
                          parameter awidth = 32)
                          parameter awidth = 32)
Line 137... Line 126...
                adr  = {awidth{1'bx}};
                adr  = {awidth{1'bx}};
                dout = {dwidth{1'bx}};
                dout = {dwidth{1'bx}};
                we   = 1'hx;
                we   = 1'hx;
                sel  = {dwidth/8{1'bx}};
                sel  = {dwidth/8{1'bx}};
                -> test_command_end;
                -> test_command_end;
 
 
        end
        end
 
 
endtask
endtask
 
 
////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////
//
//
// Wishbone read cycle
// Wishbone read cycle
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        input   [awidth   -1:0] a;
        input   [awidth   -1:0] a;
        output  [dwidth   -1:0] d;
        output  [dwidth   -1:0] d;
        input   [dwidth/8 -1:0] s;
        input   [dwidth/8 -1:0] s;
 
 
        begin
        begin
 
 
                // wait initial delay
                // wait initial delay
                repeat(delay) @(posedge clk);
                repeat(delay) @(posedge clk);
 
 
                // assert wishbone signals
                // assert wishbone signals
                #1;
                #1;
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                stb  = 1'bx;
                stb  = 1'bx;
                adr  = {awidth{1'bx}};
                adr  = {awidth{1'bx}};
                dout = {dwidth{1'bx}};
                dout = {dwidth{1'bx}};
                we   = 1'hx;
                we   = 1'hx;
                sel  = {dwidth/8{1'bx}};
                sel  = {dwidth/8{1'bx}};
 
 
        end
        end
 
 
endtask
endtask
 
 
////////////////////////////////////////////////////////////////////
////////////////////////////////////////////////////////////////////
//
//
// Wishbone compare cycle (read data from location and compare with expected data)
// Wishbone compare cycle (read data from location and compare with expected data)
Line 207... Line 195...
                  begin
                  begin
                        -> cmp_error_detect;
                        -> cmp_error_detect;
                        $display("Data compare error at address %h. Received %h, expected %h at time %t", a, q, d_exp, $time);
                        $display("Data compare error at address %h. Received %h, expected %h at time %t", a, q, d_exp, $time);
                  end
                  end
        end
        end
 
 
endtask
endtask
 
 
endmodule
endmodule
 
 
 
 

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