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[/] [xgate/] [trunk/] [rtl/] [verilog/] [xgate_irq_encode.v] - Diff between revs 28 and 67
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// 45678901234567890123456789012345678901234567890123456789012345678901234567890
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module xgate_irq_encode #(parameter MAX_CHANNEL = 127) // Max XGATE Interrupt Channel Number
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module xgate_irq_encode #(parameter MAX_CHANNEL = 127) // Max XGATE Interrupt Channel Number
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(
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(
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output reg [ 6:0] int_req, // Encoded interrupt request
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output reg [ 6:0] int_req, // Encoded interrupt request to RISC
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output [MAX_CHANNEL:0] xgif, // Interrupt outputs to Host
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input [MAX_CHANNEL:0] chan_req_i // XGATE Interrupt request
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input [MAX_CHANNEL:0] chan_req_i, // XGATE Interrupt requests from peropherials
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input [MAX_CHANNEL:0] chan_bypass, // XGATE Interrupt bypass
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input [MAX_CHANNEL:0] xgif_status // Interrupt outputs from RISC core
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);
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);
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// Set int_reg to the index of the index of the highest chen_req_i input that is active
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wire [MAX_CHANNEL:0] chan_ena_gate; // Ouptut of channel enable gating
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// Pass non-bypassed interrupt inputs to XGATE RISC
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assign chan_ena_gate = ~chan_bypass & chan_req_i;
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// Set int_reg to the index of the index of the lowest chan_req_i input that is active
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integer i = 0;
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integer i = 0;
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always @(chan_req_i)
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always @(chan_ena_gate)
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begin
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begin
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int_req = 0;
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int_req = 0;
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for (i = 0; i <= MAX_CHANNEL; i = i + 1)
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for (i = MAX_CHANNEL; i >= 0; i = i - 1)
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if (chan_req_i[i] == 1'b1)
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if (chan_ena_gate[i] == 1'b1)
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int_req = i;
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int_req = i;
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end
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end
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// XGATE output interrupt mux
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assign xgif = (chan_bypass & chan_req_i) | (~chan_bypass & xgif_status);
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endmodule // xgate_irq_encode
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endmodule // xgate_irq_encode
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