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[/] [xgate/] [trunk/] [rtl/] [verilog/] [xgate_irq_encode.v] - Diff between revs 72 and 96
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////////////////////////////////////////////////////////////////////////////////
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////////////////////////////////////////////////////////////////////////////////
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//
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//
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// Computer Operating Properly - XGATE interrupt encoder
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// XGATE Coprocessor - XGATE interrupt encoder
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//
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//
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// Author: Bob Hayes
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// Author: Bob Hayes
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// rehayes@opencores.org
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// rehayes@opencores.org
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//
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//
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// Downloaded from: http://www.opencores.org/projects/xgate.....
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// Downloaded from: http://www.opencores.org/projects/xgate.....
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input [MAX_CHANNEL:1] chan_req_i, // XGATE Interrupt requests from peropherials
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input [MAX_CHANNEL:1] chan_req_i, // XGATE Interrupt requests from peropherials
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input [MAX_CHANNEL:1] chan_bypass, // XGATE Interrupt bypass
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input [MAX_CHANNEL:1] chan_bypass, // XGATE Interrupt bypass
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input [MAX_CHANNEL:1] xgif_status // Interrupt outputs from RISC core
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input [MAX_CHANNEL:1] xgif_status // Interrupt outputs from RISC core
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);
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);
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integer i; // Loop Counter for array index
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wire [MAX_CHANNEL:1] chan_ena_gate; // Ouptut of channel enable gating
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wire [MAX_CHANNEL:1] chan_ena_gate; // Ouptut of channel enable gating
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// Pass non-bypassed interrupt inputs to XGATE RISC
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// Pass non-bypassed interrupt inputs to XGATE RISC
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assign chan_ena_gate = ~chan_bypass & chan_req_i;
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assign chan_ena_gate = ~chan_bypass & chan_req_i;
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// Set int_reg to the index of the index of the lowest chan_req_i input that is active
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// Set int_reg to the index of the index of the lowest chan_req_i input that is active
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integer i = 0;
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always @(chan_ena_gate)
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always @(chan_ena_gate)
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begin
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begin
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int_req = 0;
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int_req = 0;
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for (i = MAX_CHANNEL; i >= 1; i = i - 1)
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for (i = MAX_CHANNEL; i >= 1; i = i - 1)
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if (chan_ena_gate[i] == 1'b1)
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if (chan_ena_gate[i] == 1'b1)
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