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////////////////////////////////////////////////////////////////////////////////
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//
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// XGATE Coprocessor - XGATE JTAG Module
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//
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// Author: Robert Hayes
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// rehayes@opencores.org
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//
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// Downloaded from: http://www.opencores.org/projects/xgate.....
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//
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////////////////////////////////////////////////////////////////////////////////
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// Copyright (c) 2011, Robert Hayes
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//
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// This source file is free software: you can redistribute it and/or modify
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// it under the terms of the GNU Lesser General Public License as published
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// by the Free Software Foundation, either version 3 of the License, or
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// (at your option) any later version.
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//
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// Supplemental terms.
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// * Redistributions of source code must retain the above copyright
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// notice, this list of conditions and the following disclaimer.
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// * Neither the name of the <organization> nor the
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// names of its contributors may be used to endorse or promote products
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// derived from this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY Robert Hayes ''AS IS'' AND ANY
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// EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
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// WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
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// DISCLAIMED. IN NO EVENT SHALL Robert Hayes BE LIABLE FOR ANY
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// DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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// (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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// LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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// SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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//
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// You should have received a copy of the GNU General Public License
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// along with this program. If not, see <http://www.gnu.org/licenses/>.
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////////////////////////////////////////////////////////////////////////////////
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// 45678901234567890123456789012345678901234567890123456789012345678901234567890
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// -----------------------------------------------------------------------------
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// JTAG TAP Controller
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// -----------------------------------------------------------------------------
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module xgate_jtag #(parameter IR_BITS = 4) // Number of Instruction Register Bits
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module xgate_jtag #(parameter IR_BITS = 4) // Number of Instruction Register Bits
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(
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(
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output jtag_tdo, // JTAG Serial Output Data
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output jtag_tdo, // JTAG Serial Output Data
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output jtag_tdo_en, // JTAG Serial Output Data tri-state enable
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output jtag_tdo_en, // JTAG Serial Output Data tri-state enable
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input jtag_tdi, // JTAG Serial Input Data
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input jtag_tdi, // JTAG Serial Input Data
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input jtag_clk, // JTAG Test clock
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input jtag_clk, // JTAG Test clock
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input jtag_reset_n, // JTAG Async reset signal
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input jtag_reset_n, // JTAG Async reset signal
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input jtag_tms // JTAG Test Mode Select
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input jtag_tms, // JTAG Test Mode Select
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output extest, // JTAG Command for I/O control
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output clamp, // JTAG Command for I/O control
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output highz, // JTAG Command for I/O control
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output force_pul_lo, // JTAG Command for I/O control
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output force_pul_hi, // JTAG Command for I/O control
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output sel_bsd, // JTAG select the boundary scan register
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output sel_udi_1, // JTAG select the udi_1 (testmode control) register
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output capture_clk, // Shift and input capture clock
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output update_clk, // Load holding register
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output capture_dr, // Enable shift/capture register input loading,
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output update_dr, // Enable holding register input loading
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output shift_dr, // Select eather shift mode or parallel capture mode
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input bsd_so, // Serial data input from boundary scan chain
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input user1_so // Serial data input from user register
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);
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);
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wire [3:0] jtag_state;
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wire [3:0] jtag_state;
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wire [3:0] next_jtag_state;
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wire [3:0] next_jtag_state;
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wire update_ir;
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wire [IR_BITS-1:0] ir_reg;
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wire capture_ir;
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wire shift_ir;
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wire update_dr;
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wire capture_dr;
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wire shift_dr;
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assign jtag_tdo = 1'b1;
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assign jtag_tdo_en = 1'b0;
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// Define clocks here, future enhansment would be to add scan clock mux
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// update_clk is output I/O clock and control register capture clock
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// capture_clock is input I/O clock and shifting clock
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assign update_clk = !jtag_clk;
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assign capture_clk = jtag_clk;
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// ---------------------------------------------------------------------------
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// ---------------------------------------------------------------------------
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xgate_jtag_sm
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xgate_jtag_sm
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jtag_sm(
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jtag_sm(
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.jtag_state(jtag_state),
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.jtag_state(jtag_state),
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| Line 33... |
Line 92... |
.capture_ir(capture_ir),
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.capture_ir(capture_ir),
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.shift_ir(shift_ir),
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.shift_ir(shift_ir),
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.update_dr(update_dr),
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.update_dr(update_dr),
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.capture_dr(capture_dr),
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.capture_dr(capture_dr),
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.shift_dr(shift_dr),
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.shift_dr(shift_dr),
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.jtag_clk(jtag_clk),
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.capture_clk(capture_clk),
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.jtag_reset_n(jtag_reset_n),
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.jtag_reset_n(jtag_reset_n),
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.jtag_tms(jtag_tms)
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.jtag_tms(jtag_tms)
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);
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);
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// ---------------------------------------------------------------------------
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// ---------------------------------------------------------------------------
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xgate_jtag_ir #(.IR_BITS(IR_BITS))
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xgate_jtag_ir #(.IR_BITS(IR_BITS))
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jtag_ir(
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jtag_ir(
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.ir_reg(ir_reg),
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.ir_so(ir_so),
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.capture_clk(capture_clk),
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.update_clk(update_clk),
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.update_ir(update_ir),
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.update_ir(update_ir),
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.capture_ir(capture_ir),
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.capture_ir(capture_ir),
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.shift_ir(shift_ir),
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.shift_ir(shift_ir),
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.jtag_clk(jtag_clk),
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.jtag_tdi(jtag_tdi),
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.jtag_tdi(jtag_tdi),
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.jtag_reset_n(jtag_reset_n),
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.jtag_reset_n(jtag_reset_n)
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.jtag_tms(jtag_tms)
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);
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// ---------------------------------------------------------------------------
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xgate_instr_decode #(.IR_BITS(IR_BITS))
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decoder(
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.bypass(bypass),
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.clamp(clamp),
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.highz(highz),
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.extest(extest),
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.force_pul_lo(force_pul_lo),
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.force_pul_hi(force_pul_hi),
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.sample(sample),
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.idcode(idcode),
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.usercode(usercode),
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.udi_1(udi_1),
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.sel_bypass(sel_bypass),
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.sel_bsd(sel_bsd),
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.sel_id(sel_id),
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.sel_udi_1(sel_udi_1),
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.ir_reg(ir_reg)
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);
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);
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// ---------------------------------------------------------------------------
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// ---------------------------------------------------------------------------
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bc_2
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xgate_bypass_reg
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gpio_0_bc2(
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tdi_bypass(
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.capture_clk(),
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.bypass_so(bypass_so),
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.update_clk(),
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.capture_en(bsr_capture),
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.jtag_tdi(jtag_tdi),
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.update_en(bsr_update),
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.capture_clk(capture_clk),
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.shift_dr(bsr_shift),
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.jtag_reset_n(jtag_reset_n)
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.mode(),
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);
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.si(),
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.data_in(from_core_gpio_0),
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// ---------------------------------------------------------------------------
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.reset_n(),
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xgate_id_reg
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.data_out(to_pad_gpio_0),
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chip_id(
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.so(gpio_0_bc2_so)
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.id_so(id_so),
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.jtag_tdi(jtag_tdi),
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.capture_clk(capture_clk),
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.capture_dr(capture_dr),
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.shift_dr(shift_dr),
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.idcode(idcode),
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.usercode(usercode),
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.jtag_reset_n(jtag_reset_n)
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);
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);
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// ---------------------------------------------------------------------------
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xgate_tdo_mux
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tdo_out(
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.sel_bypass(sel_bypass),
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.sel_bsd(sel_bsd),
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.sel_id(sel_id),
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.sel_udi_1(sel_udi_1),
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.bypass_so(bypass_so),
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.bsd_so(bsd_so),
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.user1_so(user1_so),
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.id_so(id_so),
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.ir_so(ir_so),
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.shift_dr(shift_dr),
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.shift_ir(shift_ir),
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.update_clk(update_clk),
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.jtag_reset_n(jtag_reset_n),
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.jtag_tdo(jtag_tdo),
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.jtag_tdo_en(jtag_tdo_en)
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);
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endmodule // xgate_jtag
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endmodule // xgate_jtag
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// -----------------------------------------------------------------------------
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// -----------------------------------------------------------------------------
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// JTAG TAP State Machine
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// -----------------------------------------------------------------------------
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// -----------------------------------------------------------------------------
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// -----------------------------------------------------------------------------
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module xgate_jtag_sm
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module xgate_jtag_sm
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(
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(
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output reg [3:0] jtag_state, // JTAG State
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output reg [3:0] jtag_state, // JTAG State
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output reg [3:0] next_jtag_state, // Pseudo Register for JTAG next state logic
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output reg [3:0] next_jtag_state, // Pseudo Register for JTAG next state logic
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| Line 87... |
Line 199... |
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output update_dr,
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output update_dr,
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output capture_dr,
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output capture_dr,
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output shift_dr,
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output shift_dr,
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|
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input jtag_clk, // JTAG Test clock
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input capture_clk, // JTAG Test clock
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input jtag_reset_n, // JTAG Async reset signal
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input jtag_reset_n, // JTAG Async reset signal
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input jtag_tms // JTAG Test Mode Select
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input jtag_tms // JTAG Test Mode Select
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);
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);
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parameter RESET = 4'b0000,
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parameter RESET = 4'hF,
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RUN_TEST_IDLE = 4'b1000,
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RUN_TEST_IDLE = 4'hC,
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SEL_DR_SCAN = 4'b0001,
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SEL_DR_SCAN = 4'h7,
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CAPTURE_DR = 4'b0010,
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CAPTURE_DR = 4'h6,
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SHIFT_DR = 4'b0011,
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SHIFT_DR = 4'h2,
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EXIT1_DR = 4'b0100,
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EXIT1_DR = 4'h1,
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PAUSE_DR = 4'b0101,
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PAUSE_DR = 4'h3,
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EXIT2_DR = 4'b0110,
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EXIT2_DR = 4'h0,
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UPDATE_DR = 4'b0111,
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UPDATE_DR = 4'h5,
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SEL_IR_SCAN = 4'b1001,
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SEL_IR_SCAN = 4'h4,
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CAPTURE_IR = 4'b1010,
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CAPTURE_IR = 4'hE,
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SHIFT_IR = 4'b1011,
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SHIFT_IR = 4'hA,
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EXIT1_IR = 4'b1100,
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EXIT1_IR = 4'h9,
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PAUSE_IR = 4'b1101,
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PAUSE_IR = 4'hB,
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EXIT2_IR = 4'b1110,
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EXIT2_IR = 4'h8,
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UPDATE_IR = 4'b1111;
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UPDATE_IR = 4'hD;
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|
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assign update_ir = jtag_state == UPDATE_IR;
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assign update_ir = jtag_state == UPDATE_IR;
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assign capture_ir = jtag_state == CAPTURE_IR;
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assign capture_ir = jtag_state == CAPTURE_IR;
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assign shift_ir = jtag_state == SHIFT_IR;
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assign shift_ir = jtag_state == SHIFT_IR;
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Line 231... |
assign capture_dr = jtag_state == CAPTURE_DR;
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assign capture_dr = jtag_state == CAPTURE_DR;
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assign shift_dr = jtag_state == SHIFT_DR;
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assign shift_dr = jtag_state == SHIFT_DR;
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// Define the JTAG State Register
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// Define the JTAG State Register
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always @(posedge jtag_clk or negedge jtag_reset_n)
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always @(posedge capture_clk or negedge jtag_reset_n)
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if (!jtag_reset_n)
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if (!jtag_reset_n)
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jtag_state <= RESET;
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jtag_state <= RESET;
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else
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else
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jtag_state <= next_jtag_state;
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jtag_state <= next_jtag_state;
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| Line 169... |
Line 281... |
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endmodule // xgate_jtag_sm
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endmodule // xgate_jtag_sm
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// -----------------------------------------------------------------------------
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// -----------------------------------------------------------------------------
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// JTAG TAP Instruction Register
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// -----------------------------------------------------------------------------
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// -----------------------------------------------------------------------------
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// -----------------------------------------------------------------------------
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module xgate_jtag_ir #(parameter IR_BITS = 4) // Number of Instruction Register Bits
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module xgate_jtag_ir #(parameter IR_BITS = 4) // Number of Instruction Register Bits
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(
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(
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output reg [IR_BITS-1:0] ir_reg,
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output reg [IR_BITS-1:0] ir_reg,
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output ir_so, // IR shift out
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|
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input update_ir,
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input update_ir,
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input capture_ir,
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input capture_ir,
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input shift_ir,
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input shift_ir,
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|
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input jtag_tdi, // JTAG Serial Input Data
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input jtag_tdi, // JTAG Serial Input Data
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input jtag_clk, // JTAG Test clock
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input capture_clk, // JTAG Test clock
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input jtag_reset_n, // JTAG Async reset signal
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input update_clk,
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input jtag_tms // JTAG Test Mode Select
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input jtag_reset_n // JTAG Async reset signal
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);
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);
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|
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reg [IR_BITS-1:0] ir_shift_reg;
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reg [IR_BITS-1:0] ir_shift_reg;
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|
|
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assign ir_so = ir_shift_reg[0];
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|
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// JTAG Instruction Shift Register
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// JTAG Instruction Shift Register
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always @(posedge jtag_clk or negedge jtag_reset_n)
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always @(posedge capture_clk or negedge jtag_reset_n)
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if (!jtag_reset_n)
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if (!jtag_reset_n)
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ir_shift_reg <= 0;
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ir_shift_reg <= 0;
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else if (capture_ir)
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else if (capture_ir)
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ir_shift_reg <= ir_reg;
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ir_shift_reg <= ir_reg;
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else if (shift_ir)
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else if (shift_ir)
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ir_shift_reg <= {jtag_tdi, ir_shift_reg[(IR_BITS-1):1]};
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ir_shift_reg <= {jtag_tdi, ir_shift_reg[(IR_BITS-1):1]};
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|
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// JTAG Instruction Register
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// JTAG Instruction Register
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always @(posedge jtag_clk or negedge jtag_reset_n)
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always @(posedge update_clk or negedge jtag_reset_n)
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if (!jtag_reset_n)
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if (!jtag_reset_n)
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ir_reg <= 0;
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ir_reg <= {IR_BITS{1'b1}}; // Make the default instruction BYPASS
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else if (update_ir)
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else if (update_ir)
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ir_reg <= ir_shift_reg;
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ir_reg <= ir_shift_reg;
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endmodule // xgate_jtag_ir
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endmodule // xgate_jtag_ir
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// -----------------------------------------------------------------------------
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// -----------------------------------------------------------------------------
|
|
// JTAG Bypass Register
|
// -----------------------------------------------------------------------------
|
// -----------------------------------------------------------------------------
|
// -----------------------------------------------------------------------------
|
module xgate_bypass_reg
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|
(
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|
output reg bypass_so,
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|
|
|
input jtag_tdi, // JTAG Serial Input Data
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|
input capture_clk, // JTAG Test clock
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|
input jtag_reset_n // JTAG Async reset signal
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|
);
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|
|
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// JTAG Bypass Register
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always @(posedge capture_clk or negedge jtag_reset_n)
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if (!jtag_reset_n)
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bypass_so <= 0;
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else
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bypass_so <= jtag_tdi;
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|
|
module test_mode_cntrl #(parameter NUM_BITS = 10)
|
endmodule // xgate_bypass_reg
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|
|
|
|
|
// -----------------------------------------------------------------------------
|
|
// JTAG ID Register
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|
// -----------------------------------------------------------------------------
|
|
module xgate_id_reg #(parameter NUM_BITS = 32)
|
(
|
(
|
// OUTPUT
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output id_so,
|
output so,
|
|
output reg [NUM_BITS-1:0] mode_bits,
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input jtag_tdi, // JTAG Serial Input Data
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|
|
// INPUTs
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input [NUM_BITS-1:0] obs_in,
|
|
input si,
|
|
input capture_clk,
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input capture_clk,
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input update_clk,
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input capture_dr,
|
input capture_en,
|
input shift_dr,
|
input update_en,
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input idcode,
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input inst_en,
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input usercode,
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input shift_en,
|
input jtag_reset_n // JTAG Async reset signal
|
input reset_n
|
|
);
|
);
|
|
|
|
parameter user_code_val = 32'ha596_c3f0;
|
|
parameter version = 4'h1;
|
|
parameter part_num = 16'h1105;
|
|
parameter manufacture_id = 11'h00f;
|
|
|
reg [NUM_BITS-1:0] shift_reg;
|
reg [NUM_BITS-1:0] id_shifter;
|
|
|
wire [NUM_BITS-1:0] din_mux = shift_en ? {shift_reg[NUM_BITS-1:1], si} : obs_in;
|
wire [NUM_BITS-1:0] jtag_id = {version, part_num, manufacture_id, 1'b1};
|
wire [NUM_BITS-1:0] cap_mux = capture_en ? shift_reg : din_mux;
|
wire [NUM_BITS-1:0] sel_mux = ({NUM_BITS{idcode}} & jtag_id) | ({NUM_BITS{usercode}} & user_code_val);
|
wire [NUM_BITS-1:0] update_mux = update_en ? shift_reg : mode_bits;
|
wire [NUM_BITS-1:0] din_mux = shift_dr ? {jtag_tdi, id_shifter[(NUM_BITS-1):1]} : jtag_id;
|
|
|
always @(posedge capture_clk or negedge reset_n)
|
wire capture_en = (idcode || usercode) && (capture_dr || shift_dr);
|
if (!reset_n)
|
|
shift_reg <= 0;
|
|
else if (inst_en)
|
|
shift_reg <= cap_mux;
|
|
|
|
always @(posedge update_clk or negedge reset_n)
|
// JTAG Id Register
|
if (!reset_n)
|
always @(posedge capture_clk or negedge jtag_reset_n)
|
mode_bits <= 0;
|
if (!jtag_reset_n)
|
else if (inst_en)
|
id_shifter <= 0;
|
mode_bits <= update_mux;
|
else if (capture_en)
|
|
id_shifter <= din_mux;
|
|
|
assign so = shift_reg[NUM_BITS-1];
|
assign id_so = id_shifter[0];
|
|
|
endmodule //
|
endmodule // xgate_id_reg
|
|
|
|
|
// -----------------------------------------------------------------------------
|
// -----------------------------------------------------------------------------
|
|
// JTAG Instruction decoder of the IR Register
|
|
// -----------------------------------------------------------------------------
|
|
module xgate_instr_decode #(parameter IR_BITS = 4) // Number of Instruction Register Bits
|
|
(
|
|
output reg bypass,
|
|
output reg clamp,
|
|
output reg highz,
|
|
output reg extest,
|
|
output reg force_pul_lo,
|
|
output reg force_pul_hi,
|
|
output reg sample,
|
|
output reg idcode,
|
|
output reg usercode,
|
|
output reg udi_1,
|
|
|
|
output sel_bypass,
|
|
output sel_bsd,
|
|
output sel_id,
|
|
output sel_udi_1,
|
|
|
|
input [IR_BITS-1:0] ir_reg
|
|
);
|
|
|
|
assign sel_bypass = bypass || clamp || highz || force_pul_lo || force_pul_hi;
|
|
assign sel_bsd = extest || sample;
|
|
assign sel_id = idcode || usercode;
|
|
assign sel_udi_1 = udi_1;
|
|
|
|
always @*
|
|
begin
|
|
bypass = 0;
|
|
clamp = 0;
|
|
highz = 0;
|
|
extest = 0;
|
|
force_pul_lo = 0;
|
|
force_pul_hi = 0;
|
|
sample = 0;
|
|
idcode = 0;
|
|
usercode = 0;
|
|
udi_1 = 0;
|
|
casez (ir_reg)
|
|
4'b0110: clamp = 1;
|
|
4'b0101: highz = 1;
|
|
4'b0000: extest = 1;
|
|
4'b1001: force_pul_lo = 1;
|
|
4'b1010: force_pul_hi = 1;
|
|
4'b0111: sample = 1;
|
|
4'b0001: idcode = 1;
|
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4'b0011: usercode = 1;
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4'b1100: udi_1 = 1;
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|
default: bypass = 1;
|
|
endcase
|
|
end
|
|
|
|
endmodule // xgate_instr_decode
|
|
|
|
|
// -----------------------------------------------------------------------------
|
// -----------------------------------------------------------------------------
|
|
// JTAG Test Data Output mux
|
// -----------------------------------------------------------------------------
|
// -----------------------------------------------------------------------------
|
|
module xgate_tdo_mux
|
|
(
|
|
input sel_bypass,
|
|
input sel_bsd,
|
|
input sel_id,
|
|
input sel_udi_1,
|
|
|
|
input bypass_so,
|
|
input bsd_so,
|
|
input id_so,
|
|
input user1_so,
|
|
input ir_so,
|
|
|
|
input shift_dr,
|
|
input shift_ir,
|
|
input update_clk,
|
|
input jtag_reset_n,
|
|
|
|
output reg jtag_tdo,
|
|
output reg jtag_tdo_en
|
|
);
|
|
|
|
wire bypass_gate = shift_dr && sel_bypass && bypass_so;
|
|
wire bsd_gate = shift_dr && sel_bsd && bsd_so;
|
|
wire id_gate = shift_dr && sel_id && id_so;
|
|
wire udi_1_gate = shift_dr && sel_udi_1 && user1_so;
|
|
wire ir_gate = shift_ir && ir_so;
|
|
|
|
wire jtag_tdo_mux = bypass_gate || bsd_gate || id_gate || udi_1_gate || ir_gate;
|
|
|
|
// JTAG TDO Retiming Register
|
|
always @(posedge update_clk or negedge jtag_reset_n)
|
|
if (!jtag_reset_n)
|
|
jtag_tdo <= 0;
|
|
else
|
|
jtag_tdo <= jtag_tdo_mux;
|
|
|
|
// JTAG Output Enable Register
|
|
always @(posedge update_clk or negedge jtag_reset_n)
|
|
if (!jtag_reset_n)
|
|
jtag_tdo_en <= 0;
|
|
else
|
|
jtag_tdo_en <= shift_dr || shift_ir;
|
|
|
|
endmodule // xgate_tdo_mux
|
|
|
|
|
|
// -----------------------------------------------------------------------------
|
|
// Boundary Scan Cell #7
|
|
// -----------------------------------------------------------------------------
|
module bc_7
|
module bc_7
|
(
|
(
|
input capture_clk,
|
input capture_clk, // Shift and input capture clock
|
input update_clk,
|
input update_clk, // Load holding register
|
input capture_en,
|
input capture_en, // Enable shift/capture register parallel input loading,
|
input update_en,
|
input update_en, // Enable holding register input loading
|
input shift_dr,
|
input shift_dr, // Select eather shift mode or parallel capture mode
|
input mode1,
|
input mode, // Select test mode or mission mode control of pad
|
input si,
|
input si, // Serial data input
|
input pin_input,
|
input pin_input, // Mission mode input from pin
|
input control_out,
|
input control_out, // Signal from bc_2 module controlling output enable pin
|
input output_data,
|
input output_data, // mission mode data in from core
|
input reset_n,
|
input reset_n, // reset
|
|
|
output ic_input,
|
output data_out, // Final data to pad
|
output data_out,
|
output reg so // Serial data out
|
output reg so
|
|
);
|
);
|
|
|
reg data_reg;
|
reg data_reg;
|
reg enable_reg;
|
|
reg control_reg;
|
|
reg so_0;
|
|
|
|
// Shift register
|
// Shift register
|
always @(posedge capture_clk or negedge reset_n)
|
always @(posedge capture_clk or negedge reset_n)
|
if (!reset_n)
|
if (!reset_n)
|
so <= 0;
|
so <= 0;
|
else if (capture_en)
|
else if (capture_en)
|
so <= shift_dr ? si : ((!control_out || mode1) ? pin_input : output_data);
|
so <= shift_dr ? si : ((!control_out || mode) ? pin_input : output_data);
|
|
|
// Holding register
|
// Holding register
|
always @(posedge update_clk or negedge reset_n)
|
always @(posedge update_clk or negedge reset_n)
|
if (!reset_n)
|
if (!reset_n)
|
data_reg <= 0;
|
data_reg <= 0;
|
| Line 302... |
Line 535... |
|
|
endmodule // bc_7
|
endmodule // bc_7
|
|
|
|
|
// -----------------------------------------------------------------------------
|
// -----------------------------------------------------------------------------
|
|
// Boundary Scan Cell #2
|
// -----------------------------------------------------------------------------
|
// -----------------------------------------------------------------------------
|
// -----------------------------------------------------------------------------
|
|
|
|
module bc_2
|
module bc_2
|
(
|
(
|
input capture_clk, // Shift and input capture clock
|
input capture_clk, // Shift and input capture clock
|
input update_clk, // Load holding register
|
input update_clk, // Load holding register
|
input capture_en, // Enable shift/capture register input loading,
|
input capture_en, // Enable shift/capture register parallel input loading
|
input update_en, // Enable holding register input loading
|
input update_en, // Enable holding register input loading
|
input shift_dr, // Select eather shift mode or parallel capture mode
|
input shift_dr, // Select eather shift mode or parallel capture mode
|
input mode, // Select test mode or mission mode output
|
input mode, // Select test mode or mission mode control of pad
|
input si, // Serial data input
|
input si, // Serial data input
|
input data_in, // Mission mode input
|
input data_in, // Mission mode input
|
input reset_n, // reset
|
input reset_n, // reset
|
|
|
output data_out, // Final data to pad
|
output data_out, // Final data to pad
|
| Line 341... |
Line 573... |
|
|
assign data_out = mode ? data_reg : data_in;
|
assign data_out = mode ? data_reg : data_in;
|
|
|
endmodule // bc_2
|
endmodule // bc_2
|
|
|
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|
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|
|
|
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|
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No newline at end of file
|
