| Line 60... |
Line 60... |
output reg clear_xgif_2, // Strobe for decode to clear interrupt flag bank 2
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output reg clear_xgif_2, // Strobe for decode to clear interrupt flag bank 2
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output reg clear_xgif_1, // Strobe for decode to clear interrupt flag bank 1
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output reg clear_xgif_1, // Strobe for decode to clear interrupt flag bank 1
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output reg clear_xgif_0, // Strobe for decode to clear interrupt flag bank 0
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output reg clear_xgif_0, // Strobe for decode to clear interrupt flag bank 0
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output reg [15:0] clear_xgif_data, // Data for decode to clear interrupt flag
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output reg [15:0] clear_xgif_data, // Data for decode to clear interrupt flag
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output semaph_stat, // Return Status of Semaphore bit
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output semaph_stat, // Return Status of Semaphore bit
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output reg brk_irq_ena, // Enable BRK instruction to generate interrupt
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|
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input bus_clk, // Control register bus clock
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input bus_clk, // Control register bus clock
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input async_rst_b, // Async reset signal
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input async_rst_b, // Async reset signal
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input sync_reset, // Syncronous reset signal
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input sync_reset, // Syncronous reset signal
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input cop_flag, // COP Rollover Flag
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input cop_flag, // COP Rollover Flag
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| Line 105... |
Line 106... |
xge <= 1'b0;
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xge <= 1'b0;
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xgfrz <= 1'b0;
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xgfrz <= 1'b0;
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xgdbg <= 1'b0;
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xgdbg <= 1'b0;
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xgss <= 1'b0;
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xgss <= 1'b0;
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xgfact <= 1'b0;
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xgfact <= 1'b0;
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brk_irq_ena <= 1'b0;
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xgsweif_c <= 1'b0;
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xgsweif_c <= 1'b0;
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xgie <= 1'b0;
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xgie <= 1'b0;
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end
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end
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else if (sync_reset)
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else if (sync_reset)
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begin
|
begin
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xge <= 1'b0;
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xge <= 1'b0;
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xgfrz <= 1'b0;
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xgfrz <= 1'b0;
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xgdbg <= 1'b0;
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xgdbg <= 1'b0;
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xgss <= 1'b0;
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xgss <= 1'b0;
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xgfact <= 1'b0;
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xgfact <= 1'b0;
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brk_irq_ena <= 1'b0;
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xgsweif_c <= 1'b0;
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xgsweif_c <= 1'b0;
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xgie <= 1'b0;
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xgie <= 1'b0;
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end
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end
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else if (write_xgmctl)
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else if (write_xgmctl)
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begin
|
begin
|
xge <= write_bus[15] ? write_bus[7] : xge;
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xge <= write_bus[15] ? write_bus[7] : xge;
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xgfrz <= write_bus[14] ? write_bus[6] : xgfrz;
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xgfrz <= write_bus[14] ? write_bus[6] : xgfrz;
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xgdbg <= write_bus[13] ? write_bus[5] : xgdbg;
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xgdbg <= write_bus[13] ? write_bus[5] : xgdbg;
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xgss <= write_bus[13] ? write_bus[4] : xgss;
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xgss <= write_bus[12] && write_bus[4];
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xgfact <= write_bus[12] ? write_bus[3] : xgfact;
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xgfact <= write_bus[11] ? write_bus[3] : xgfact;
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xgsweif_c <= write_bus[10] ? write_bus[1] : xgsweif_c;
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brk_irq_ena <= write_bus[10] ? write_bus[2] : brk_irq_ena;
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xgie <= write_bus[ 9] ? write_bus[0] : xgie;
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xgsweif_c <= write_bus[ 9] && write_bus[1];
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xgie <= write_bus[ 8] ? write_bus[0] : xgie;
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end
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end
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else
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else
|
begin
|
begin
|
xgss <= 1'b0;
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xgss <= 1'b0;
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xgsweif_c <= 1'b0;
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xgsweif_c <= 1'b0;
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