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module xgate_regs #(parameter ARST_LVL = 1'b0, // asynchronous reset level
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module xgate_regs #(parameter ARST_LVL = 1'b0, // asynchronous reset level
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parameter MAX_CHANNEL = 127) // Max XGATE Interrupt Channel Number
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parameter MAX_CHANNEL = 127) // Max XGATE Interrupt Channel Number
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(
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(
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output reg xge, // XGATE Module Enable
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output reg xge, // XGATE Module Enable
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output reg xgfrz, // Stop XGATE in Freeze Mode
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output reg xgfrz, // Stop XGATE in Freeze Mode
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output reg xgdbg, // XGATE Debug Mode
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output reg xgdbg_set, // Enter XGATE Debug Mode
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output reg xgdbg_clear, // Leave XGATE Debug Mode
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output reg xgss, // XGATE Single Step
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output reg xgss, // XGATE Single Step
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output reg xgfact, // XGATE Flag Activity
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output reg xgfact, // XGATE Flag Activity
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output reg xgsweif_c, // Clear XGATE Software Error Interrupt FLag
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output reg xgsweif_c, // Clear XGATE Software Error Interrupt FLag
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output reg xgie, // XGATE Interrupt Enable
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output reg xgie, // XGATE Interrupt Enable
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output reg [15:1] xgvbr, // XGATE vector Base Address Register
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output reg [15:1] xgvbr, // XGATE vector Base Address Register
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//
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//
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// generate wishbone write registers
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// generate wishbone write registers
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// XGMCTL Register
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// XGMCTL Register
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// xgdbgm; // XGATE Debug Mode Mask
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always @(posedge bus_clk or negedge async_rst_b)
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always @(posedge bus_clk or negedge async_rst_b)
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if (!async_rst_b)
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if (!async_rst_b)
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begin
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begin
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xge <= 1'b0;
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xge <= 1'b0;
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xgfrz <= 1'b0;
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xgfrz <= 1'b0;
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xgdbg <= 1'b0;
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xgdbg_set <= 1'b0;
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xgdbg_clear <= 1'b0;
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xgss <= 1'b0;
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xgss <= 1'b0;
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xgfact <= 1'b0;
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xgfact <= 1'b0;
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brk_irq_ena <= 1'b0;
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brk_irq_ena <= 1'b0;
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xgsweif_c <= 1'b0;
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xgsweif_c <= 1'b0;
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xgie <= 1'b0;
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xgie <= 1'b0;
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end
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end
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else if (sync_reset)
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else if (sync_reset)
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begin
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begin
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xge <= 1'b0;
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xge <= 1'b0;
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xgfrz <= 1'b0;
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xgfrz <= 1'b0;
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xgdbg <= 1'b0;
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xgdbg_set <= 1'b0;
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xgdbg_clear <= 1'b0;
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xgss <= 1'b0;
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xgss <= 1'b0;
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xgfact <= 1'b0;
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xgfact <= 1'b0;
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brk_irq_ena <= 1'b0;
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brk_irq_ena <= 1'b0;
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xgsweif_c <= 1'b0;
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xgsweif_c <= 1'b0;
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xgie <= 1'b0;
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xgie <= 1'b0;
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end
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end
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else if (write_xgmctl)
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else if (write_xgmctl)
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begin
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begin
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xge <= write_bus[15] ? write_bus[7] : xge;
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xge <= write_bus[15] ? write_bus[7] : xge;
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xgfrz <= write_bus[14] ? write_bus[6] : xgfrz;
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xgfrz <= write_bus[14] ? write_bus[6] : xgfrz;
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xgdbg <= write_bus[13] ? write_bus[5] : xgdbg;
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xgdbg_set <= write_bus[13] && write_bus[5];
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xgdbg_clear <= write_bus[13] && !write_bus[5];
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xgss <= write_bus[12] && write_bus[4];
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xgss <= write_bus[12] && write_bus[4];
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xgfact <= write_bus[11] ? write_bus[3] : xgfact;
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xgfact <= write_bus[11] ? write_bus[3] : xgfact;
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brk_irq_ena <= write_bus[10] ? write_bus[2] : brk_irq_ena;
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brk_irq_ena <= write_bus[10] ? write_bus[2] : brk_irq_ena;
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xgsweif_c <= write_bus[ 9] && write_bus[1];
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xgsweif_c <= write_bus[ 9] && write_bus[1];
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xgie <= write_bus[ 8] ? write_bus[0] : xgie;
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xgie <= write_bus[ 8] ? write_bus[0] : xgie;
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end
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end
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else
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else
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begin
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begin
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xgss <= 1'b0;
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xgss <= 1'b0;
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xgsweif_c <= 1'b0;
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xgsweif_c <= 1'b0;
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xgdbg_set <= 1'b0;
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xgdbg_clear <= 1'b0;
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end
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end
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// XGVBR Register
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// XGVBR Register
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always @(posedge bus_clk or negedge async_rst_b)
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always @(posedge bus_clk or negedge async_rst_b)
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if (!async_rst_b)
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if (!async_rst_b)
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