| Line 49... |
Line 49... |
output reg xgfact, // XGATE Flag Activity
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output reg xgfact, // XGATE Flag Activity
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output reg xgsweif_c, // Clear XGATE Software Error Interrupt FLag
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output reg xgsweif_c, // Clear XGATE Software Error Interrupt FLag
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output reg xgie, // XGATE Interrupt Enable
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output reg xgie, // XGATE Interrupt Enable
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output reg [15:1] xgvbr, // XGATE vector Base Address Register
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output reg [15:1] xgvbr, // XGATE vector Base Address Register
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output reg [ 7:0] xgswt, // XGATE Software Trigger Register for host
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output reg [ 7:0] xgswt, // XGATE Software Trigger Register for host
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output reg [15:0] xgisp74, // XGATE Interrupt level 7-4 stack pointer
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output reg [15:0] xgisp30, // XGATE Interrupt level 3-0 stack pointer
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output reg clear_xgif_7, // Strobe for decode to clear interrupt flag bank 7
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output reg clear_xgif_7, // Strobe for decode to clear interrupt flag bank 7
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output reg clear_xgif_6, // Strobe for decode to clear interrupt flag bank 6
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output reg clear_xgif_6, // Strobe for decode to clear interrupt flag bank 6
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output reg clear_xgif_5, // Strobe for decode to clear interrupt flag bank 5
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output reg clear_xgif_5, // Strobe for decode to clear interrupt flag bank 5
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output reg clear_xgif_4, // Strobe for decode to clear interrupt flag bank 4
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output reg clear_xgif_4, // Strobe for decode to clear interrupt flag bank 4
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output reg clear_xgif_3, // Strobe for decode to clear interrupt flag bank 3
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output reg clear_xgif_3, // Strobe for decode to clear interrupt flag bank 3
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| Line 68... |
Line 66... |
input bus_clk, // Control register bus clock
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input bus_clk, // Control register bus clock
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input async_rst_b, // Async reset signal
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input async_rst_b, // Async reset signal
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input sync_reset, // Syncronous reset signal
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input sync_reset, // Syncronous reset signal
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input [15:0] write_bus, // Write Data Bus
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input [15:0] write_bus, // Write Data Bus
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input write_xgmctl, // Write Strobe for XGMCTL register
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input write_xgmctl, // Write Strobe for XGMCTL register
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input write_xgisp74, // Write Strobe for XGISP74 register
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input write_xgisp30, // Write Strobe for XGISP30 register
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input [ 1:0] write_xgvbr, // Write Strobe for XGVBR register
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input [ 1:0] write_xgvbr, // Write Strobe for XGVBR register
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input [ 1:0] write_xgif_7, // Write Strobe for Interrupt Flag Register 7
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input [ 1:0] write_xgif_7, // Write Strobe for Interrupt Flag Register 7
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input [ 1:0] write_xgif_6, // Write Strobe for Interrupt Flag Register 6
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input [ 1:0] write_xgif_6, // Write Strobe for Interrupt Flag Register 6
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input [ 1:0] write_xgif_5, // Write Strobe for Interrupt Flag Register 5
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input [ 1:0] write_xgif_5, // Write Strobe for Interrupt Flag Register 5
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input [ 1:0] write_xgif_4, // Write Strobe for Interrupt Flag Register 4
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input [ 1:0] write_xgif_4, // Write Strobe for Interrupt Flag Register 4
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| Line 156... |
Line 152... |
begin
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begin
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xgvbr[15:8] <= write_xgvbr[1] ? write_bus[15:8] : xgvbr[15:8];
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xgvbr[15:8] <= write_xgvbr[1] ? write_bus[15:8] : xgvbr[15:8];
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xgvbr[ 7:1] <= write_xgvbr[0] ? write_bus[ 7:1] : xgvbr[ 7:1];
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xgvbr[ 7:1] <= write_xgvbr[0] ? write_bus[ 7:1] : xgvbr[ 7:1];
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end
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end
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// XGISP74 Register
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always @(posedge bus_clk or negedge async_rst_b)
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if (!async_rst_b)
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xgisp74 <= 16'b0;
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else if (sync_reset)
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xgisp74 <= 16'b0;
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else if (write_xgisp74)
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xgisp74 <= xge ? xgisp74 : write_bus;
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// XGISP30 Register
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always @(posedge bus_clk or negedge async_rst_b)
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if (!async_rst_b)
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xgisp30 <= 16'b0;
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else if (sync_reset)
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xgisp30 <= 16'b0;
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else if (write_xgisp30)
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xgisp30 <= xge ? xgisp30 : write_bus;
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// XGIF 7-0 Registers
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// XGIF 7-0 Registers
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assign write_any_xgif = write_xgif_7 | write_xgif_6 | write_xgif_5 | write_xgif_4 |
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assign write_any_xgif = write_xgif_7 | write_xgif_6 | write_xgif_5 | write_xgif_4 |
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write_xgif_3 | write_xgif_2 | write_xgif_1 | write_xgif_0;
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write_xgif_3 | write_xgif_2 | write_xgif_1 | write_xgif_0;
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// Registers to clear the interrupt flags. Decode a specific interrupt to
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// Registers to clear the interrupt flags. Decode a specific interrupt to
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