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[/] [xgate/] [trunk/] [rtl/] [verilog/] [xgate_regs.v] - Diff between revs 42 and 53
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| Rev 42 |
Rev 53 |
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Line 75... |
input [ 1:0] write_xgif_4, // Write Strobe for Interrupt Flag Register 4
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input [ 1:0] write_xgif_4, // Write Strobe for Interrupt Flag Register 4
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input [ 1:0] write_xgif_3, // Write Strobe for Interrupt Flag Register 3
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input [ 1:0] write_xgif_3, // Write Strobe for Interrupt Flag Register 3
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input [ 1:0] write_xgif_2, // Write Strobe for Interrupt Flag Register 2
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input [ 1:0] write_xgif_2, // Write Strobe for Interrupt Flag Register 2
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input [ 1:0] write_xgif_1, // Write Strobe for Interrupt Flag Register 1
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input [ 1:0] write_xgif_1, // Write Strobe for Interrupt Flag Register 1
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input [ 1:0] write_xgif_0, // Write Strobe for Interrupt Flag Register 0
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input [ 1:0] write_xgif_0, // Write Strobe for Interrupt Flag Register 0
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input write_xgswt // Write Strobe for XGSWT register
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input write_xgswt, // Write Strobe for XGSWT register
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input debug_ack // Clear debug register
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);
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// registers
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// registers
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Line 133... |
end
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end
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else
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else
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begin
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begin
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xgss <= 1'b0;
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xgss <= 1'b0;
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xgsweif_c <= 1'b0;
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xgsweif_c <= 1'b0;
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xgdbg_set <= 1'b0;
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xgdbg_set <= xgdbg_set && !debug_ack;
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xgdbg_clear <= 1'b0;
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xgdbg_clear <= 1'b0;
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end
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end
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// XGVBR Register
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// XGVBR Register
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always @(posedge bus_clk or negedge async_rst_b)
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always @(posedge bus_clk or negedge async_rst_b)
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