| Line 60... |
Line 60... |
output reg clear_xgif_1, // Strobe for decode to clear interrupt flag bank 1
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output reg clear_xgif_1, // Strobe for decode to clear interrupt flag bank 1
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output reg clear_xgif_0, // Strobe for decode to clear interrupt flag bank 0
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output reg clear_xgif_0, // Strobe for decode to clear interrupt flag bank 0
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output reg [15:0] clear_xgif_data, // Data for decode to clear interrupt flag
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output reg [15:0] clear_xgif_data, // Data for decode to clear interrupt flag
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output semaph_stat, // Return Status of Semaphore bit
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output semaph_stat, // Return Status of Semaphore bit
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output reg brk_irq_ena, // Enable BRK instruction to generate interrupt
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output reg brk_irq_ena, // Enable BRK instruction to generate interrupt
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output [MAX_CHANNEL:0] chan_bypass, // XGATE Interrupt enable or bypass
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output reg [127:0] irq_bypass, // Register to hold irq bypass control state
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input bus_clk, // Control register bus clock
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input bus_clk, // Control register bus clock
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input async_rst_b, // Async reset signal
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input async_rst_b, // Async reset signal
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input sync_reset, // Syncronous reset signal
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input sync_reset, // Syncronous reset signal
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input [15:0] write_bus, // Write Data Bus
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input [15:0] write_bus, // Write Data Bus
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| Line 75... |
Line 77... |
input [ 1:0] write_xgif_4, // Write Strobe for Interrupt Flag Register 4
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input [ 1:0] write_xgif_4, // Write Strobe for Interrupt Flag Register 4
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input [ 1:0] write_xgif_3, // Write Strobe for Interrupt Flag Register 3
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input [ 1:0] write_xgif_3, // Write Strobe for Interrupt Flag Register 3
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input [ 1:0] write_xgif_2, // Write Strobe for Interrupt Flag Register 2
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input [ 1:0] write_xgif_2, // Write Strobe for Interrupt Flag Register 2
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input [ 1:0] write_xgif_1, // Write Strobe for Interrupt Flag Register 1
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input [ 1:0] write_xgif_1, // Write Strobe for Interrupt Flag Register 1
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input [ 1:0] write_xgif_0, // Write Strobe for Interrupt Flag Register 0
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input [ 1:0] write_xgif_0, // Write Strobe for Interrupt Flag Register 0
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input [ 1:0] write_irw_en_7, // Write Strobe for Interrupt Bypass Control Register 7
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input [ 1:0] write_irw_en_6, // Write Strobe for Interrupt Bypass Control Register 6
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input [ 1:0] write_irw_en_5, // Write Strobe for Interrupt Bypass Control Register 5
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input [ 1:0] write_irw_en_4, // Write Strobe for Interrupt Bypass Control Register 4
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input [ 1:0] write_irw_en_3, // Write Strobe for Interrupt Bypass Control Register 3
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input [ 1:0] write_irw_en_2, // Write Strobe for Interrupt Bypass Control Register 2
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input [ 1:0] write_irw_en_1, // Write Strobe for Interrupt Bypass Control Register 1
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input [ 1:0] write_irw_en_0, // Write Strobe for Interrupt Bypass Control Register 0
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input write_xgswt, // Write Strobe for XGSWT register
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input write_xgswt, // Write Strobe for XGSWT register
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input debug_ack // Clear debug register
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input debug_ack // Clear debug register
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);
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);
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integer j; // Loop counter for channel bypass counter assigments
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integer k; // Loop counter for channel bypass counter assigments
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// registers
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// registers
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reg [127:0] irq_bypass_d; // Pseudo regester for routing address and data to irq bypass register
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// Wires
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// Wires
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wire [ 1:0] write_any_xgif;
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wire [ 1:0] write_any_xgif;
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//
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//
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| Line 206... |
Line 220... |
if (!async_rst_b)
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if (!async_rst_b)
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xgswt <= 8'h00;
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xgswt <= 8'h00;
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else if (sync_reset)
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else if (sync_reset)
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xgswt <= 8'h00;
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xgswt <= 8'h00;
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else if (write_xgswt)
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else if (write_xgswt)
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xgswt <= (write_bus[15:8] & write_bus[7:0]) | (~write_bus[15:8] & xgswt[7:0]);
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// Channel Bypass Register input bits
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always @*
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begin
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begin
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xgswt[7] <= write_bus[15] ? write_bus[7] : xgswt[7];
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k = 0;
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xgswt[6] <= write_bus[14] ? write_bus[6] : xgswt[6];
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for (j = 0; j <= 127; j = j + 1)
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xgswt[5] <= write_bus[13] ? write_bus[5] : xgswt[5];
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begin
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xgswt[4] <= write_bus[11] ? write_bus[4] : xgswt[4];
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if (j <= MAX_CHANNEL)
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xgswt[3] <= write_bus[12] ? write_bus[3] : xgswt[3];
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begin
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xgswt[2] <= write_bus[10] ? write_bus[2] : xgswt[2];
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if ((j >= 0) && (j < 8))
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xgswt[1] <= write_bus[ 9] ? write_bus[1] : xgswt[1];
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irq_bypass_d[j] = write_irw_en_0[0] ? write_bus[k] : irq_bypass[j];
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xgswt[0] <= write_bus[ 8] ? write_bus[0] : xgswt[0];
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if ((j >= 8) && (j < 16))
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irq_bypass_d[j] = write_irw_en_0[1] ? write_bus[k] : irq_bypass[j];
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if ((j >= 16) && (j < 24))
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irq_bypass_d[j] = write_irw_en_1[0] ? write_bus[k] : irq_bypass[j];
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if ((j >= 24) && (j < 32))
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irq_bypass_d[j] = write_irw_en_1[1] ? write_bus[k] : irq_bypass[j];
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if ((j >= 32) && (j < 40))
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irq_bypass_d[j] = write_irw_en_2[0] ? write_bus[k] : irq_bypass[j];
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if ((j >= 40) && (j < 48))
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irq_bypass_d[j] = write_irw_en_2[1] ? write_bus[k] : irq_bypass[j];
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if ((j >= 48) && (j < 56))
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irq_bypass_d[j] = write_irw_en_3[0] ? write_bus[k] : irq_bypass[j];
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if ((j >= 56) && (j < 64))
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irq_bypass_d[j] = write_irw_en_3[1] ? write_bus[k] : irq_bypass[j];
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if ((j >= 64) && (j < 72))
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irq_bypass_d[j] = write_irw_en_4[0] ? write_bus[k] : irq_bypass[j];
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if ((j >= 72) && (j < 80))
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irq_bypass_d[j] = write_irw_en_4[1] ? write_bus[k] : irq_bypass[j];
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if ((j >= 80) && (j < 88))
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irq_bypass_d[j] = write_irw_en_5[0] ? write_bus[k] : irq_bypass[j];
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if ((j >= 88) && (j < 96))
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irq_bypass_d[j] = write_irw_en_5[1] ? write_bus[k] : irq_bypass[j];
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if ((j >= 96) && (j < 104))
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irq_bypass_d[j] = write_irw_en_6[0] ? write_bus[k] : irq_bypass[j];
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if ((j >= 104) && (j < 112))
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irq_bypass_d[j] = write_irw_en_6[1] ? write_bus[k] : irq_bypass[j];
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if ((j >= 112) && (j < 120))
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irq_bypass_d[j] = write_irw_en_7[0] ? write_bus[k] : irq_bypass[j];
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if ((j >= 120) && (j < 128))
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irq_bypass_d[j] = write_irw_en_7[1] ? write_bus[k] : irq_bypass[j];
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end
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else
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irq_bypass_d[j] = 1'b0;
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k = k + 1;
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if (k > 15)
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k = 0;
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end
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end
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end
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// Channel Bypass Registers
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// Synthesys should eliminate bits that with D input tied to zero
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always @(posedge bus_clk or negedge async_rst_b)
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if ( !async_rst_b )
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irq_bypass <= {128{1'b1}};
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else
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irq_bypass <= irq_bypass_d;
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// Alias the register name to the output pin name so only the used bit are carried out
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// assign chan_bypass = {(MAX_CHANNEL+1){1'b1}};
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assign chan_bypass = irq_bypass[MAX_CHANNEL:0];
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endmodule // xgate_regs
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endmodule // xgate_regs
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No newline at end of file
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No newline at end of file
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