| Line 60... |
Line 60... |
output reg clear_xgif_1, // Strobe for decode to clear interrupt flag bank 1
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output reg clear_xgif_1, // Strobe for decode to clear interrupt flag bank 1
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output reg clear_xgif_0, // Strobe for decode to clear interrupt flag bank 0
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output reg clear_xgif_0, // Strobe for decode to clear interrupt flag bank 0
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output reg [15:0] clear_xgif_data, // Data for decode to clear interrupt flag
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output reg [15:0] clear_xgif_data, // Data for decode to clear interrupt flag
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output semaph_stat, // Return Status of Semaphore bit
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output semaph_stat, // Return Status of Semaphore bit
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output reg brk_irq_ena, // Enable BRK instruction to generate interrupt
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output reg brk_irq_ena, // Enable BRK instruction to generate interrupt
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output [MAX_CHANNEL:0] chan_bypass, // XGATE Interrupt enable or bypass
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output [MAX_CHANNEL:1] chan_bypass, // XGATE Interrupt enable or bypass
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output reg [127:0] irq_bypass, // Register to hold irq bypass control state
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output reg [127:1] irq_bypass, // Register to hold irq bypass control state
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input bus_clk, // Control register bus clock
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input bus_clk, // Control register bus clock
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input async_rst_b, // Async reset signal
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input async_rst_b, // Async reset signal
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input sync_reset, // Syncronous reset signal
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input sync_reset, // Syncronous reset signal
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input [15:0] write_bus, // Write Data Bus
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input [15:0] write_bus, // Write Data Bus
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| Line 94... |
Line 94... |
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integer j; // Loop counter for channel bypass counter assigments
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integer j; // Loop counter for channel bypass counter assigments
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integer k; // Loop counter for channel bypass counter assigments
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integer k; // Loop counter for channel bypass counter assigments
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// registers
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// registers
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reg [127:0] irq_bypass_d; // Pseudo regester for routing address and data to irq bypass register
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reg [127:1] irq_bypass_d; // Pseudo regester for routing address and data to irq bypass register
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// Wires
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// Wires
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wire [ 1:0] write_any_xgif;
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wire [ 1:0] write_any_xgif;
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//
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//
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| Line 226... |
Line 226... |
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// Channel Bypass Register input bits
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// Channel Bypass Register input bits
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always @*
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always @*
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begin
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begin
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k = 0;
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k = 1; // WISHBONE Bus bit counter [15:0]
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for (j = 0; j <= 127; j = j + 1)
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for (j = 1; j <= 127; j = j + 1)
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begin
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begin
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if (j <= MAX_CHANNEL)
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if (j <= MAX_CHANNEL)
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begin
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begin
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if ((j >= 0) && (j < 8))
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if ((j >= 0) && (j < 8))
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irq_bypass_d[j] = write_irw_en_0[0] ? write_bus[k] : irq_bypass[j];
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irq_bypass_d[j] = write_irw_en_0[0] ? write_bus[k] : irq_bypass[j];
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| Line 276... |
Line 276... |
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// Channel Bypass Registers
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// Channel Bypass Registers
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// Synthesys should eliminate bits that with D input tied to zero
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// Synthesys should eliminate bits that with D input tied to zero
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always @(posedge bus_clk or negedge async_rst_b)
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always @(posedge bus_clk or negedge async_rst_b)
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if ( !async_rst_b )
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if ( !async_rst_b )
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irq_bypass <= {128{1'b1}};
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irq_bypass <= {127{1'b1}};
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else
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else
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irq_bypass <= irq_bypass_d;
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irq_bypass <= irq_bypass_d;
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// Alias the register name to the output pin name so only the used bit are carried out
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// Alias the register name to the output pin name so only the used bit are carried out
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// assign chan_bypass = {(MAX_CHANNEL+1){1'b1}};
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assign chan_bypass = irq_bypass[MAX_CHANNEL:1];
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assign chan_bypass = irq_bypass[MAX_CHANNEL:0];
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endmodule // xgate_regs
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endmodule // xgate_regs
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No newline at end of file
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No newline at end of file
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