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[/] [xgate/] [trunk/] [rtl/] [verilog/] [xgate_regs.v] - Diff between revs 89 and 92

Rev 89	Rev 92
Line 277...	Line 277...
`// Channel Bypass Registers`	`// Channel Bypass Registers`
`// Synthesys should eliminate bits that with D input tied to zero`	`// Synthesys should eliminate bits that with D input tied to zero`
`always @(posedge bus_clk or negedge async_rst_b)`	`always @(posedge bus_clk or negedge async_rst_b)`
`if ( !async_rst_b )`	`if ( !async_rst_b )`
`irq_bypass <= {127{1'b1}};`	`irq_bypass <= {127{1'b1}};`
	`else if (sync_reset)`
	`irq_bypass <= {127{1'b1}};`
`else`	`else`
`irq_bypass <= irq_bypass_d;`	`irq_bypass <= irq_bypass_d;`

`// Alias the register name to the output pin name so only the used bit are carried out`	`// Alias the register name to the output pin name so only the used bit are carried out`
`assign chan_bypass = irq_bypass[MAX_CHANNEL:1];`	`assign chan_bypass = irq_bypass[MAX_CHANNEL:1];`